/*
 * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
 * 
 * SPDX-License-Identifier: Apache-2.0
 * 
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * 
 * http://www.apache.org/licenses/LICENSE-2.0
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * @file     cw32f030.h
 * @brief    CMSIS HeaderFile
 * @version  1.2
 * @date     22. July 2021
 * @note     Generated by SVDConv V3.3.25 on Thursday, 22.07.2021 14:07:41
 *           from File 'cw32f030.svd',
 *           last modified on Thursday, 22.07.2021 06:07:37
 */



/** @addtogroup CW Co.Ltd
  * @{
  */


/** @addtogroup cw32f030
  * @{
  */


#ifndef CW32F030_H
#define CW32F030_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M0+ Specific Interrupt Numbers  ======================================= */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ==========================================  cw32f030 Specific Interrupt Numbers  ========================================== */
  WDT_IRQn                  =   0,              /*!< 0  Watch Dog Timer Interrupt                                              */
  LVD_IRQn                  =   1,              /*!< 1  Low Voltage Detect Interrupt                                           */
  RTC_IRQn                  =   2,              /*!< 2  Real Time Clock Interrupt                                              */
  FLASHRAM_IRQn             =   3,              /*!< 3  Flash/RAM Interrupt                                                    */
  RCC_IRQn                  =   4,              /*!< 4  RCC Interupt                                                           */
  GPIOA_IRQn                =   5,              /*!< 5  GPIOA Interrupt                                                        */
  GPIOB_IRQn                =   6,              /*!< 6  GPIOB Interrupt                                                        */
  GPIOC_IRQn                =   7,              /*!< 7  GPIOC Interrupt                                                        */
  GPIOF_IRQn                =   8,              /*!< 8  GPIOF Interrupt                                                        */
  DMACH1_IRQn               =   9,              /*!< 9  DMA Channel 1 Interrupt                                                */
  DMACH23_IRQn              =  10,              /*!< 10 DMA Channel 2/3 Interrupt                                              */
  DMACH45_IRQn              =  11,              /*!< 11 DMA Channel 2/3 Interrupt                                              */
  ADC_IRQn                  =  12,              /*!< 12 ADC Interrupt                                                          */
  ATIM_IRQn                 =  13,              /*!< 13 Advanced Timer Interrupt                                               */
  VC1_IRQn                  =  14,              /*!< 14 Voltage Comparator 1 Interrupt                                         */
  VC2_IRQn                  =  15,              /*!< 15 Voltage Comparator 2 Interrupt                                         */
  GTIM1_IRQn                =  16,              /*!< 16 General Timer1 Interrupt                                               */
  GTIM2_IRQn                =  17,              /*!< 17 General Timer2 Interrupt                                               */
  GTIM3_IRQn                =  18,              /*!< 18 General Timer3 Interrupt                                               */
  GTIM4_IRQn                =  19,              /*!< 19 General Timer4 Interrupt                                               */
  BTIM1_IRQn                =  20,              /*!< 20 Base Timer1 Interrupt                                                  */
  BTIM2_IRQn                =  21,              /*!< 21 Base Timer2 Interrupt                                                  */
  BTIM3_IRQn                =  22,              /*!< 22 Base Timer3 Interrupt                                                  */
  I2C1_IRQn                 =  23,              /*!< 23 I2C1 Interrupt                                                         */
  I2C2_IRQn                 =  24,              /*!< 24 I2C2 Interrput                                                         */
  SPI1_IRQn                 =  25,              /*!< 25 SPI1 Interrupt                                                         */
  SPI2_IRQn                 =  26,              /*!< 26 SPI2 Interrupt                                                         */
  UART1_IRQn                =  27,              /*!< 27 UART1 Interrupt                                                        */
  UART2_IRQn                =  28,              /*!< 28 UART2 Interrupt                                                        */
  UART3_IRQn                =  29,              /*!< 29 UART3 Interrupt                                                        */
  AWT_IRQn                  =  30,              /*!< 30 Auto Wakeup Timer Interrupt                                            */
  FAULT_IRQn                =  31               /*!< 31 FAULT Interrupt                                                        */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ==========================  Configuration of the ARM Cortex-M0+ Processor and Core Peripherals  =========================== */
#define __CM0PLUS_REV                 0x0001U   /*!< CM0PLUS Core Revision                                                     */
#define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
#define __MPU_PRESENT                  0        /*!< MPU present                                                               */
#define __FPU_PRESENT                  0        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0plus.h"                       /*!< ARM Cortex-M0+ processor and core peripherals                             */
#include "system_cw32f030.h"                    /*!< cw32f030 System                                                           */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc ADC (ADC)
  */

typedef struct {                                /*!< (@ 0x40012400) ADC Structure                                              */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) Control register0                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t MODE       : 3;            /*!< [3..1] desc MODE                                                          */
      __IOM uint32_t BGREN      : 1;            /*!< [4..4] desc BGREN                                                         */
      __IOM uint32_t TSEN       : 1;            /*!< [5..5] desc TSEN                                                          */
      __IOM uint32_t REF        : 2;            /*!< [7..6] desc REF                                                           */
      __IOM uint32_t CLK        : 3;            /*!< [10..8] desc CLK                                                          */
      __IOM uint32_t SAM        : 2;            /*!< [12..11] desc SAM                                                         */
      __IOM uint32_t BUF        : 1;            /*!< [13..13] desc BUF                                                         */
      __IOM uint32_t BIAS       : 2;            /*!< [15..14] desc BIAS                                                        */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) Control register1                                          */
    
    struct {
      __IOM uint32_t CHMUX      : 4;            /*!< [3..0] desc CHMUX                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t DISCARD    : 1;            /*!< [5..5] desc DISCARD                                                       */
      __IOM uint32_t ALIGN      : 1;            /*!< [6..6] desc ALIGN                                                         */
      __IOM uint32_t DMAEN      : 1;            /*!< [7..7] desc DMAEN                                                         */
      __IOM uint32_t WDTCH      : 4;            /*!< [11..8] desc WDTCH                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t WDTALL     : 1;            /*!< [13..13] desc WDTALL                                                      */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t START;                       /*!< (@ 0x00000008) desc START                                                 */
    
    struct {
      __IOM uint32_t START      : 1;            /*!< [0..0] desc START                                                         */
      __IOM uint32_t AUTOSTOP   : 1;            /*!< [1..1] desc AUTOSTOP                                                      */
    } START_f;
  } ;
  
  union {
    __IOM uint32_t SQR;                         /*!< (@ 0x0000000C) desc SQR                                                   */
    
    struct {
      __IOM uint32_t SQR0       : 4;            /*!< [3..0] desc SQR0                                                          */
      __IOM uint32_t SQR1       : 4;            /*!< [7..4] desc SQR1                                                          */
      __IOM uint32_t SQR2       : 4;            /*!< [11..8] desc SQR2                                                         */
      __IOM uint32_t SQR3       : 4;            /*!< [15..12] desc SQR3                                                        */
      __IOM uint32_t ENS        : 2;            /*!< [17..16] desc ENS                                                         */
    } SQR_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000010) Control register2                                          */
    
    struct {
      __IOM uint32_t CNT        : 8;            /*!< [7..0] desc CNT                                                           */
      __IOM uint32_t ACCEN      : 1;            /*!< [8..8] desc ACCEN                                                         */
      __IOM uint32_t ACCRST     : 1;            /*!< [9..9] desc ACCRST                                                        */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t VTH;                         /*!< (@ 0x00000014) desc VTH                                                   */
    
    struct {
      __IOM uint32_t VTH        : 12;           /*!< [11..0] desc VTH                                                          */
    } VTH_f;
  } ;
  
  union {
    __IOM uint32_t VTL;                         /*!< (@ 0x00000018) desc VTL                                                   */
    
    struct {
      __IOM uint32_t VTL        : 12;           /*!< [11..0] desc VTL                                                          */
    } VTL_f;
  } ;
  
  union {
    __IOM uint32_t TRIGGER;                     /*!< (@ 0x0000001C) desc TRIGGER                                               */
    
    struct {
      __IOM uint32_t ATIM       : 1;            /*!< [0..0] desc ATIM                                                          */
      __IOM uint32_t GTIM1      : 1;            /*!< [1..1] desc GTIM1                                                         */
      __IOM uint32_t GTIM2      : 1;            /*!< [2..2] desc GTIM2                                                         */
      __IOM uint32_t GTIM3      : 1;            /*!< [3..3] desc GTIM3                                                         */
      __IOM uint32_t GTIM4      : 1;            /*!< [4..4] desc GTIM4                                                         */
      __IOM uint32_t BTIM1      : 1;            /*!< [5..5] desc BTIM1                                                         */
      __IOM uint32_t BTIM2      : 1;            /*!< [6..6] desc BTIM2                                                         */
      __IOM uint32_t BTIM3      : 1;            /*!< [7..7] desc BTIM3                                                         */
      __IOM uint32_t UART1      : 1;            /*!< [8..8] desc UART1                                                         */
      __IOM uint32_t UART2      : 1;            /*!< [9..9] desc UART2                                                         */
      __IOM uint32_t UART3      : 1;            /*!< [10..10] desc UART3                                                       */
      __IOM uint32_t SPI1       : 1;            /*!< [11..11] desc SPI1                                                        */
      __IOM uint32_t SPI2       : 1;            /*!< [12..12] desc SPI2                                                        */
      __IOM uint32_t I2C1       : 1;            /*!< [13..13] desc I2C1                                                        */
      __IOM uint32_t I2C2       : 1;            /*!< [14..14] desc I2C2                                                        */
      __IOM uint32_t DMA        : 1;            /*!< [15..15] desc DMA                                                         */
    } TRIGGER_f;
  } ;
  
  union {
    __IM  uint32_t RESULT0;                     /*!< (@ 0x00000020) desc RESULT0                                               */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT0_f;
  } ;
  
  union {
    __IM  uint32_t RESULT1;                     /*!< (@ 0x00000024) desc RESULT1                                               */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT1_f;
  } ;
  
  union {
    __IM  uint32_t RESULT2;                     /*!< (@ 0x00000028) desc RESULT2                                               */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT2_f;
  } ;
  
  union {
    __IM  uint32_t RESULT3;                     /*!< (@ 0x0000002C) desc RESULT3                                               */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT3_f;
  } ;
  
  union {
    __IM  uint32_t RESULTACC;                   /*!< (@ 0x00000030) desc RESULTACC                                             */
    
    struct {
      __IM  uint32_t RESULT     : 24;           /*!< [23..0] desc RESULT                                                       */
    } RESULTACC_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000034) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t EOC        : 1;            /*!< [0..0] desc EOC                                                           */
      __IOM uint32_t EOS        : 1;            /*!< [1..1] desc EOS                                                           */
      __IOM uint32_t EOA        : 1;            /*!< [2..2] desc EOA                                                           */
      __IOM uint32_t WDTL       : 1;            /*!< [3..3] desc WDTL                                                          */
      __IOM uint32_t WDTH       : 1;            /*!< [4..4] desc WDTH                                                          */
      __IOM uint32_t WDTR       : 1;            /*!< [5..5] desc WDTR                                                          */
      __IOM uint32_t OVW        : 1;            /*!< [6..6] desc OVW                                                           */
    } IER_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000038) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t EOC        : 1;            /*!< [0..0] desc EOC                                                           */
      __IOM uint32_t EOS        : 1;            /*!< [1..1] desc EOS                                                           */
      __IOM uint32_t EOA        : 1;            /*!< [2..2] desc EOA                                                           */
      __IOM uint32_t WDTL       : 1;            /*!< [3..3] desc WDTL                                                          */
      __IOM uint32_t WDTH       : 1;            /*!< [4..4] desc WDTH                                                          */
      __IOM uint32_t WDTR       : 1;            /*!< [5..5] desc WDTR                                                          */
      __IOM uint32_t OVW        : 1;            /*!< [6..6] desc OVW                                                           */
    } ICR_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x0000003C) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t EOC        : 1;            /*!< [0..0] desc EOC                                                           */
      __IM  uint32_t EOS        : 1;            /*!< [1..1] desc EOS                                                           */
      __IM  uint32_t EOA        : 1;            /*!< [2..2] desc EOA                                                           */
      __IM  uint32_t WDTL       : 1;            /*!< [3..3] desc WDTL                                                          */
      __IM  uint32_t WDTH       : 1;            /*!< [4..4] desc WDTH                                                          */
      __IM  uint32_t WDTR       : 1;            /*!< [5..5] desc WDTR                                                          */
      __IM  uint32_t OVW        : 1;            /*!< [6..6] desc OVW                                                           */
      __IM  uint32_t READY      : 1;            /*!< [7..7] desc READY                                                         */
    } ISR_f;
  } ;
  
  union {
    __IM  uint32_t RESULT140;                   /*!< (@ 0x00000040) desc RESULT140                                             */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT140_f;
  } ;
  
  union {
    __IM  uint32_t RESULT141;                   /*!< (@ 0x00000044) desc RESULT141                                             */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT141_f;
  } ;
  
  union {
    __IM  uint32_t RESULT142;                   /*!< (@ 0x00000048) desc RESULT142                                             */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT142_f;
  } ;
  
  union {
    __IM  uint32_t RESULT143;                   /*!< (@ 0x0000004C) desc RESULT143                                             */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT143_f;
  } ;
  __IM  uint32_t  RESERVED[14];
  
  union {
    __OM  uint32_t ENABLE14;                    /*!< (@ 0x00000088) desc ENABLE14                                              */
    
    struct {
      __OM  uint32_t KEY        : 16;           /*!< [15..0] desc KEY                                                          */
    } ENABLE14_f;
  } ;
} ADC_TypeDef;                                     /*!< Size = 140 (0x8c)                                                         */



/* =========================================================================================================================== */
/* ================                                           ATIM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc ATIM (ATIM)
  */

typedef struct {                                /*!< (@ 0x40012C00) ATIM Structure                                             */
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x00000000) desc ARR                                                   */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000004) desc CNT                                                   */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
    } CNT_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x0000000C) desc CR                                                    */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t COMP       : 1;            /*!< [1..1] desc COMP                                                          */
      __IOM uint32_t CT         : 1;            /*!< [2..2] desc CT                                                            */
      __IOM uint32_t PWM2S      : 1;            /*!< [3..3] desc PWM2S                                                         */
      __IOM uint32_t PRS        : 3;            /*!< [6..4] desc PRS                                                           */
      __IOM uint32_t BUFPEN     : 1;            /*!< [7..7] desc BUFPEN                                                        */
      __IM  uint32_t            : 2;
      __IOM uint32_t UIE        : 1;            /*!< [10..10] desc UIE                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t MODE       : 2;            /*!< [13..12] Please keep 10/11                                                */
      __IOM uint32_t ONESHOT    : 1;            /*!< [14..14] desc ONESHOT                                                     */
      __IM  uint32_t            : 1;
      __IOM uint32_t OCCS       : 1;            /*!< [16..16] desc OCCS                                                        */
      __IOM uint32_t URS        : 1;            /*!< [17..17] desc URS                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t TIE        : 1;            /*!< [19..19] desc TIE                                                         */
      __IOM uint32_t BIE        : 1;            /*!< [20..20] desc BIE                                                         */
      __IOM uint32_t CISA       : 2;            /*!< [22..21] desc CISA                                                        */
      __IOM uint32_t OCCE       : 1;            /*!< [23..23] desc OCCE                                                        */
      __IOM uint32_t TG         : 1;            /*!< [24..24] desc TG                                                          */
      __IOM uint32_t UG         : 1;            /*!< [25..25] desc UG                                                          */
      __IOM uint32_t BG         : 1;            /*!< [26..26] desc BG                                                          */
      __IOM uint32_t DIR        : 1;            /*!< [27..27] desc DIR                                                         */
      __IOM uint32_t OVE        : 1;            /*!< [28..28] desc OVE                                                         */
      __IOM uint32_t UNDE       : 1;            /*!< [29..29] desc UNDE                                                        */
    } CR_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000010) desc ISR                                                   */
    
    struct {
      __IM  uint32_t UIF        : 1;            /*!< [0..0] desc UIF                                                           */
      __IM  uint32_t            : 1;
      __IM  uint32_t C1AF       : 1;            /*!< [2..2] desc C1AF                                                          */
      __IM  uint32_t C2AF       : 1;            /*!< [3..3] desc C2AF                                                          */
      __IM  uint32_t C3AF       : 1;            /*!< [4..4] desc C3AF                                                          */
      __IM  uint32_t C1BF       : 1;            /*!< [5..5] desc C1BF                                                          */
      __IM  uint32_t C2BF       : 1;            /*!< [6..6] desc C2BF                                                          */
      __IM  uint32_t C3BF       : 1;            /*!< [7..7] desc C3BF                                                          */
      __IM  uint32_t C1AE       : 1;            /*!< [8..8] desc C1AE                                                          */
      __IM  uint32_t C2AE       : 1;            /*!< [9..9] desc C2AE                                                          */
      __IM  uint32_t C3AE       : 1;            /*!< [10..10] desc C3AE                                                        */
      __IM  uint32_t C1BE       : 1;            /*!< [11..11] desc C1BE                                                        */
      __IM  uint32_t C2BE       : 1;            /*!< [12..12] desc C2BE                                                        */
      __IM  uint32_t C3BE       : 1;            /*!< [13..13] desc C3BE                                                        */
      __IM  uint32_t BIF        : 1;            /*!< [14..14] desc BIF                                                         */
      __IM  uint32_t TIF        : 1;            /*!< [15..15] desc TIF                                                         */
      __IM  uint32_t OVF        : 1;            /*!< [16..16] desc OVF                                                         */
      __IM  uint32_t UNDF       : 1;            /*!< [17..17] desc UNDF                                                        */
      __IM  uint32_t C4AF       : 1;            /*!< [18..18] desc C4AF                                                        */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000014) desc ICR                                                   */
    
    struct {
      __IOM uint32_t UIF        : 1;            /*!< [0..0] desc UIF                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t C1AF       : 1;            /*!< [2..2] desc C1AF                                                          */
      __IOM uint32_t C2AF       : 1;            /*!< [3..3] desc C2AF                                                          */
      __IOM uint32_t C3AF       : 1;            /*!< [4..4] desc C3AF                                                          */
      __IOM uint32_t C1BF       : 1;            /*!< [5..5] desc C1BF                                                          */
      __IOM uint32_t C2BF       : 1;            /*!< [6..6] desc C2BF                                                          */
      __IOM uint32_t C3BF       : 1;            /*!< [7..7] desc C3BF                                                          */
      __IOM uint32_t C1AE       : 1;            /*!< [8..8] desc C1AE                                                          */
      __IOM uint32_t C2AE       : 1;            /*!< [9..9] desc C2AE                                                          */
      __IOM uint32_t C3AE       : 1;            /*!< [10..10] desc C3AE                                                        */
      __IOM uint32_t C1BE       : 1;            /*!< [11..11] desc C1BE                                                        */
      __IOM uint32_t C2BE       : 1;            /*!< [12..12] desc C2BE                                                        */
      __IOM uint32_t C3BE       : 1;            /*!< [13..13] desc C3BE                                                        */
      __IOM uint32_t BIF        : 1;            /*!< [14..14] desc BIF                                                         */
      __IOM uint32_t TIF        : 1;            /*!< [15..15] desc TIF                                                         */
      __IOM uint32_t OVF        : 1;            /*!< [16..16] desc OVF                                                         */
      __IOM uint32_t UNDF       : 1;            /*!< [17..17] desc UNDF                                                        */
      __IOM uint32_t C4AF       : 1;            /*!< [18..18] desc C4AF                                                        */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t MSCR;                        /*!< (@ 0x00000018) desc MSCR                                                  */
    
    struct {
      __IOM uint32_t MMS        : 3;            /*!< [2..0] desc MMS                                                           */
      __IOM uint32_t CCDS       : 1;            /*!< [3..3] desc CCDS                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t TS         : 3;            /*!< [7..5] desc TS                                                            */
      __IOM uint32_t SMS        : 3;            /*!< [10..8] desc SMS                                                          */
      __IOM uint32_t IA1S       : 1;            /*!< [11..11] desc IA1S                                                        */
      __IOM uint32_t IB1S       : 1;            /*!< [12..12] desc IB1S                                                        */
    } MSCR_f;
  } ;
  
  union {
    __IOM uint32_t FLTR;                        /*!< (@ 0x0000001C) desc FLTR                                                  */
    
    struct {
      __IOM uint32_t OCM1AFLT1A : 3;            /*!< [2..0] desc OCM1AFLT1A                                                    */
      __IOM uint32_t CCP1A      : 1;            /*!< [3..3] desc CCP1A                                                         */
      __IOM uint32_t OCM1BFLT1B : 3;            /*!< [6..4] desc OCM1BFLT1B                                                    */
      __IOM uint32_t CCP1B      : 1;            /*!< [7..7] desc CCP1B                                                         */
      __IOM uint32_t OCM2AFLT2A : 3;            /*!< [10..8] desc OCM2AFLT2A                                                   */
      __IOM uint32_t CCP2A      : 1;            /*!< [11..11] desc CCP2A                                                       */
      __IOM uint32_t OCM2BFLT2B : 3;            /*!< [14..12] desc OCM2BFLT2B                                                  */
      __IOM uint32_t CCP2B      : 1;            /*!< [15..15] desc CCP2B                                                       */
      __IOM uint32_t OCM3AFLT3A : 3;            /*!< [18..16] desc OCM3AFLT3A                                                  */
      __IOM uint32_t CCP3A      : 1;            /*!< [19..19] desc CCP3A                                                       */
      __IOM uint32_t OCM3BFLT3B : 3;            /*!< [22..20] desc OCM3BFLT3B                                                  */
      __IOM uint32_t CCP3B      : 1;            /*!< [23..23] desc CCP3B                                                       */
      __IOM uint32_t FLTBK      : 3;            /*!< [26..24] desc FLTBK                                                       */
      __IOM uint32_t BKP        : 1;            /*!< [27..27] desc BKP                                                         */
      __IOM uint32_t FLTET      : 3;            /*!< [30..28] desc FLTET                                                       */
      __IOM uint32_t ETP        : 1;            /*!< [31..31] desc ETP                                                         */
    } FLTR_f;
  } ;
  
  union {
    __IOM uint32_t TRIG;                        /*!< (@ 0x00000020) desc TRIG                                                  */
    
    struct {
      __IOM uint32_t UEVE       : 1;            /*!< [0..0] desc UEVE                                                          */
      __IOM uint32_t CM1AE      : 1;            /*!< [1..1] desc CM1AE                                                         */
      __IOM uint32_t CM2AE      : 1;            /*!< [2..2] desc CM2AE                                                         */
      __IOM uint32_t CM3AE      : 1;            /*!< [3..3] desc CM3AE                                                         */
      __IOM uint32_t CM1BE      : 1;            /*!< [4..4] desc CM1BE                                                         */
      __IOM uint32_t CM2BE      : 1;            /*!< [5..5] desc CM2BE                                                         */
      __IOM uint32_t CM3BE      : 1;            /*!< [6..6] desc CM3BE                                                         */
      __IOM uint32_t ADTE       : 1;            /*!< [7..7] desc ADTE                                                          */
    } TRIG_f;
  } ;
  
  union {
    __IOM uint32_t CH1CR;                       /*!< (@ 0x00000024) desc CH1CR                                                 */
    
    struct {
      __IOM uint32_t BKSA       : 2;            /*!< [1..0] desc BKSA                                                          */
      __IOM uint32_t BKSB       : 2;            /*!< [3..2] desc BKSB                                                          */
      __IOM uint32_t CSA        : 1;            /*!< [4..4] desc CSA                                                           */
      __IOM uint32_t CSB        : 1;            /*!< [5..5] desc CSB                                                           */
      __IOM uint32_t BUFEA      : 1;            /*!< [6..6] desc BUFEA                                                         */
      __IOM uint32_t BUFEB      : 1;            /*!< [7..7] desc BUFEB                                                         */
      __IOM uint32_t CIEA       : 1;            /*!< [8..8] desc CIEA                                                          */
      __IOM uint32_t CIEB       : 1;            /*!< [9..9] desc CIEB                                                          */
      __IOM uint32_t CDEA       : 1;            /*!< [10..10] desc CDEA                                                        */
      __IOM uint32_t CDEB       : 1;            /*!< [11..11] desc CDEB                                                        */
      __IOM uint32_t CISB       : 2;            /*!< [13..12] desc CISB                                                        */
      __IOM uint32_t CCGA       : 1;            /*!< [14..14] desc CCGA                                                        */
      __IOM uint32_t CCGB       : 1;            /*!< [15..15] desc CCGB                                                        */
    } CH1CR_f;
  } ;
  
  union {
    __IOM uint32_t CH2CR;                       /*!< (@ 0x00000028) desc CH2CR                                                 */
    
    struct {
      __IOM uint32_t BKSA       : 2;            /*!< [1..0] desc BKSA                                                          */
      __IOM uint32_t BKSB       : 2;            /*!< [3..2] desc BKSB                                                          */
      __IOM uint32_t CSA        : 1;            /*!< [4..4] desc CSA                                                           */
      __IOM uint32_t CSB        : 1;            /*!< [5..5] desc CSB                                                           */
      __IOM uint32_t BUFEA      : 1;            /*!< [6..6] desc BUFEA                                                         */
      __IOM uint32_t BUFEB      : 1;            /*!< [7..7] desc BUFEB                                                         */
      __IOM uint32_t CIEA       : 1;            /*!< [8..8] desc CIEA                                                          */
      __IOM uint32_t CIEB       : 1;            /*!< [9..9] desc CIEB                                                          */
      __IOM uint32_t CDEA       : 1;            /*!< [10..10] desc CDEA                                                        */
      __IOM uint32_t CDEB       : 1;            /*!< [11..11] desc CDEB                                                        */
      __IOM uint32_t CISB       : 2;            /*!< [13..12] desc CISB                                                        */
      __IOM uint32_t CCGA       : 1;            /*!< [14..14] desc CCGA                                                        */
      __IOM uint32_t CCGB       : 1;            /*!< [15..15] desc CCGB                                                        */
    } CH2CR_f;
  } ;
  
  union {
    __IOM uint32_t CH3CR;                       /*!< (@ 0x0000002C) desc CH3CR                                                 */
    
    struct {
      __IOM uint32_t BKSA       : 2;            /*!< [1..0] desc BKSA                                                          */
      __IOM uint32_t BKSB       : 2;            /*!< [3..2] desc BKSB                                                          */
      __IOM uint32_t CSA        : 1;            /*!< [4..4] desc CSA                                                           */
      __IOM uint32_t CSB        : 1;            /*!< [5..5] desc CSB                                                           */
      __IOM uint32_t BUFEA      : 1;            /*!< [6..6] desc BUFEA                                                         */
      __IOM uint32_t BUFEB      : 1;            /*!< [7..7] desc BUFEB                                                         */
      __IOM uint32_t CIEA       : 1;            /*!< [8..8] desc CIEA                                                          */
      __IOM uint32_t CIEB       : 1;            /*!< [9..9] desc CIEB                                                          */
      __IOM uint32_t CDEA       : 1;            /*!< [10..10] desc CDEA                                                        */
      __IOM uint32_t CDEB       : 1;            /*!< [11..11] desc CDEB                                                        */
      __IOM uint32_t CISB       : 2;            /*!< [13..12] desc CISB                                                        */
      __IOM uint32_t CCGA       : 1;            /*!< [14..14] desc CCGA                                                        */
      __IOM uint32_t CCGB       : 1;            /*!< [15..15] desc CCGB                                                        */
    } CH3CR_f;
  } ;
  
  union {
    __IOM uint32_t DTR;                         /*!< (@ 0x00000030) desc DTR                                                   */
    
    struct {
      __IOM uint32_t DTR        : 8;            /*!< [7..0] desc DTR                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t DTEN       : 1;            /*!< [9..9] desc DTEN                                                          */
      __IOM uint32_t BKE        : 1;            /*!< [10..10] desc BKE                                                         */
      __IOM uint32_t AOE        : 1;            /*!< [11..11] desc AOE                                                         */
      __IOM uint32_t MOE        : 1;            /*!< [12..12] desc MOE                                                         */
      __IOM uint32_t SAFEEN     : 1;            /*!< [13..13] desc SAFEEN                                                      */
      __IOM uint32_t VCE        : 1;            /*!< [14..14] desc VCE                                                         */
    } DTR_f;
  } ;
  
  union {
    __IOM uint32_t RCR;                         /*!< (@ 0x00000034) desc RCR                                                   */
    
    struct {
      __IOM uint32_t RCR        : 8;            /*!< [7..0] desc RCR                                                           */
      __IOM uint32_t OV         : 1;            /*!< [8..8] desc OV                                                            */
      __IOM uint32_t UD         : 1;            /*!< [9..9] desc UD                                                            */
    } RCR_f;
  } ;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t CH1CCRA;                     /*!< (@ 0x0000003C) desc CH1CCRA                                               */
    
    struct {
      __IOM uint32_t CCR1A      : 16;           /*!< [15..0] desc CCR1A                                                        */
    } CH1CCRA_f;
  } ;
  
  union {
    __IOM uint32_t CH1CCRB;                     /*!< (@ 0x00000040) desc CH1CCRB                                               */
    
    struct {
      __IOM uint32_t CCR1B      : 16;           /*!< [15..0] desc CCR1B                                                        */
    } CH1CCRB_f;
  } ;
  
  union {
    __IOM uint32_t CH2CCRA;                     /*!< (@ 0x00000044) desc CH2CCRA                                               */
    
    struct {
      __IOM uint32_t CCR2A      : 16;           /*!< [15..0] desc CCR2A                                                        */
    } CH2CCRA_f;
  } ;
  
  union {
    __IOM uint32_t CH2CCRB;                     /*!< (@ 0x00000048) desc CH2CCRB                                               */
    
    struct {
      __IOM uint32_t CCR2B      : 16;           /*!< [15..0] desc CCR2B                                                        */
    } CH2CCRB_f;
  } ;
  
  union {
    __IOM uint32_t CH3CCRA;                     /*!< (@ 0x0000004C) desc CH3CCRA                                               */
    
    struct {
      __IOM uint32_t CCR3A      : 16;           /*!< [15..0] desc CCR3A                                                        */
    } CH3CCRA_f;
  } ;
  
  union {
    __IOM uint32_t CH3CCRB;                     /*!< (@ 0x00000050) desc CH3CCRB                                               */
    
    struct {
      __IOM uint32_t CCR3B      : 16;           /*!< [15..0] desc CCR3B                                                        */
    } CH3CCRB_f;
  } ;
  
  union {
    __IOM uint32_t CH4CCR;                      /*!< (@ 0x00000054) desc CH4CCR                                                */
    
    struct {
      __IOM uint32_t CCR4       : 16;           /*!< [15..0] desc CCR4                                                         */
    } CH4CCR_f;
  } ;
  
  union {
    __IOM uint32_t CH4CR;                       /*!< (@ 0x00000058) desc CH4CR                                                 */
    
    struct {
      __IOM uint32_t BUFE       : 1;            /*!< [0..0] desc BUFE                                                          */
      __IOM uint32_t CIE        : 1;            /*!< [1..1] desc CIE                                                           */
      __IOM uint32_t CDE        : 1;            /*!< [2..2] desc CDE                                                           */
      __IOM uint32_t CIS        : 2;            /*!< [4..3] desc CIS                                                           */
      __IOM uint32_t C4EN       : 1;            /*!< [5..5] desc C4EN                                                          */
    } CH4CR_f;
  } ;
} ATIM_TypeDef;                                    /*!< Size = 92 (0x5c)                                                          */



/* =========================================================================================================================== */
/* ================                                            AWT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc AWT (AWT)
  */

typedef struct {                                /*!< (@ 0x40014C00) AWT Structure                                              */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Control register                                           */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t MD         : 2;            /*!< [2..1] desc MD                                                            */
      __IM  uint32_t            : 1;
      __IOM uint32_t PRS        : 4;            /*!< [7..4] desc PRS                                                           */
      __IOM uint32_t SRC        : 3;            /*!< [10..8] desc SRC                                                          */
    } CR_f;
  } ;
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x00000004) Auto reload register                                       */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IM  uint32_t CNT;                         /*!< (@ 0x00000008) counter                                                    */
    
    struct {
      __IM  uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
    } CNT_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000010) Interrupt enable register                                  */
    
    struct {
      __IM  uint32_t            : 3;
      __IOM uint32_t UD         : 1;            /*!< [3..3] desc UD                                                            */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000014) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t            : 3;
      __IM  uint32_t UD         : 1;            /*!< [3..3] desc UD                                                            */
    } ISR_f;
  } ;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x0000001C) Interrupt flag clear register                              */
    
    struct {
      __IM  uint32_t            : 3;
      __IOM uint32_t UD         : 1;            /*!< [3..3] desc UD                                                            */
    } ICR_f;
  } ;
} AWT_TypeDef;                                     /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                           BTIM1                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Base Timer 1 (BTIM1)
  */

typedef struct {                                /*!< (@ 0x40014800) BTIM1 Structure                                            */
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x00000000) Auto Reload Register                                       */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000004) Counter Register                                           */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
    } CNT_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t ACR;                         /*!< (@ 0x0000000C) Advanced Control register                                  */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t ETRFLT     : 3;            /*!< [6..4] desc ETRFLT                                                        */
    } ACR_f;
  } ;
  
  union {
    __IOM uint32_t BCR;                         /*!< (@ 0x00000010) Base Control register                                      */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t MODE       : 2;            /*!< [2..1] desc MODE                                                          */
      __IOM uint32_t TRS        : 1;            /*!< [3..3] desc TRS                                                           */
      __IOM uint32_t POL        : 1;            /*!< [4..4] desc POL                                                           */
      __IOM uint32_t ONESHOT    : 1;            /*!< [5..5] desc ONESHOT                                                       */
      __IOM uint32_t TOGEN      : 1;            /*!< [6..6] desc TOGEN                                                         */
      __IOM uint32_t PRS        : 4;            /*!< [10..7] desc PRS                                                          */
      __IM  uint32_t PRSSTATUS  : 4;            /*!< [14..11] desc PRSSTATUS                                                   */
    } BCR_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000014) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t OV         : 1;            /*!< [0..0] desc OV                                                            */
      __IOM uint32_t TI         : 1;            /*!< [1..1] desc TI                                                            */
      __IOM uint32_t TOP        : 1;            /*!< [2..2] desc TOP                                                           */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000018) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t OV         : 1;            /*!< [0..0] desc OV                                                            */
      __IM  uint32_t TI         : 1;            /*!< [1..1] desc TI                                                            */
      __IM  uint32_t TOP        : 1;            /*!< [2..2] desc TOP                                                           */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x0000001C) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t OV         : 1;            /*!< [0..0] desc OV                                                            */
      __IOM uint32_t TI         : 1;            /*!< [1..1] desc TI                                                            */
      __IOM uint32_t TOP        : 1;            /*!< [2..2] desc TOP                                                           */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t DMA;                         /*!< (@ 0x00000020) DMA control register                                       */
    
    struct {
      __IOM uint32_t OV         : 1;            /*!< [0..0] desc OV                                                            */
      __IOM uint32_t TRS        : 1;            /*!< [1..1] desc TRS                                                           */
    } DMA_f;
  } ;
} BTIM_TypeDef;                                    /*!< Size = 36 (0x24)                                                          */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc CRC (CRC)
  */

typedef struct {                                /*!< (@ 0x40023000) CRC Structure                                              */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Control register                                           */
    
    struct {
      __IOM uint32_t MODE       : 4;            /*!< [3..0] desc MODE                                                          */
    } CR_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    union {
      __IOM uint32_t DR32;                      /*!< (@ 0x00000008) Data register                                              */
      
      struct {
        __IOM uint32_t DR32     : 32;           /*!< [31..0] desc DR32                                                         */
      } DR32_f;
    } ;
    
    union {
      __IOM uint16_t DR16;                      /*!< (@ 0x00000008) Data register                                              */
      
      struct {
        __IOM uint16_t DR16     : 16;           /*!< [15..0] desc DR16                                                         */
      } DR16_f;
    } ;
    
    union {
      __IOM uint8_t DR8;                        /*!< (@ 0x00000008) Data register                                              */
      
      struct {
        __IOM uint8_t DR8       : 8;            /*!< [7..0] desc DR8                                                           */
      } DR8_f;
    } ;
  };
  
  union {
    union {
      __IM  uint32_t RESULT32;                  /*!< (@ 0x0000000C) Result register                                            */
      
      struct {
        __IM  uint32_t RESULT32 : 32;           /*!< [31..0] desc RESULT32                                                     */
      } RESULT32_f;
    } ;
    
    union {
      __IM  uint16_t RESULT16;                  /*!< (@ 0x0000000C) Result register                                            */
      
      struct {
        __IM  uint16_t RESULT16 : 16;           /*!< [15..0] desc RESULT16                                                     */
      } RESULT16_f;
    } ;
  };
} CRC_TypeDef;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc DMA (DMA)
  */

typedef struct {                                /*!< (@ 0x40020000) DMA Structure                                              */
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000000) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t TC1        : 1;            /*!< [0..0] desc TC1                                                           */
      __IM  uint32_t TE1        : 1;            /*!< [1..1] desc TE1                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t TC2        : 1;            /*!< [4..4] desc TC2                                                           */
      __IM  uint32_t TE2        : 1;            /*!< [5..5] desc TE2                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t TC3        : 1;            /*!< [8..8] desc TC3                                                           */
      __IM  uint32_t TE3        : 1;            /*!< [9..9] desc TE3                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t TC4        : 1;            /*!< [12..12] desc TC4                                                         */
      __IM  uint32_t TE4        : 1;            /*!< [13..13] desc TE4                                                         */
      __IM  uint32_t            : 2;
      __IM  uint32_t TC5        : 1;            /*!< [16..16] desc TC5                                                         */
      __IM  uint32_t TE5        : 1;            /*!< [17..17] desc TE5                                                         */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000004) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t TC1        : 1;            /*!< [0..0] desc TC1                                                           */
      __IOM uint32_t TE1        : 1;            /*!< [1..1] desc TE1                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t TC2        : 1;            /*!< [4..4] desc TC2                                                           */
      __IOM uint32_t TE2        : 1;            /*!< [5..5] desc TE2                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t TC3        : 1;            /*!< [8..8] desc TC3                                                           */
      __IOM uint32_t TE3        : 1;            /*!< [9..9] desc TE3                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t TC4        : 1;            /*!< [12..12] desc TC4                                                         */
      __IOM uint32_t TE4        : 1;            /*!< [13..13] desc TE4                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t TC5        : 1;            /*!< [16..16] desc TC5                                                         */
      __IOM uint32_t TE5        : 1;            /*!< [17..17] desc TE5                                                         */
    } ICR_f;
  } ;
  __IM  uint32_t  RESERVED[6];
  
  union {
    __IOM uint32_t CSR1;                        /*!< (@ 0x00000020) Channel1 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IM  uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
    } CSR1_f;
  } ;
  
  union {
    __IOM uint32_t CNT1;                        /*!< (@ 0x00000024) Channel1 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT1_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR1;                    /*!< (@ 0x00000028) Channel1 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR1_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR1;                    /*!< (@ 0x0000002C) Channel1 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR1_f;
  } ;
  
  union {
    __IOM uint32_t TRIG1;                       /*!< (@ 0x00000030) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG1_f;
  } ;
  __IM  uint32_t  RESERVED1[3];
  
  union {
    __IOM uint32_t CSR2;                        /*!< (@ 0x00000040) Channel2 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IM  uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
    } CSR2_f;
  } ;
  
  union {
    __IOM uint32_t CNT2;                        /*!< (@ 0x00000044) Channel2 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT2_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR2;                    /*!< (@ 0x00000048) Channel2 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR2_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR2;                    /*!< (@ 0x0000004C) Channel2 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR2_f;
  } ;
  
  union {
    __IOM uint32_t TRIG2;                       /*!< (@ 0x00000050) Channel2 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG2_f;
  } ;
  __IM  uint32_t  RESERVED2[3];
  
  union {
    __IOM uint32_t CSR3;                        /*!< (@ 0x00000060) Channel3 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IM  uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
    } CSR3_f;
  } ;
  
  union {
    __IOM uint32_t CNT3;                        /*!< (@ 0x00000064) Channel3 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT3_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR3;                    /*!< (@ 0x00000068) Channel3 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR3_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR3;                    /*!< (@ 0x0000006C) Channel3 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR3_f;
  } ;
  
  union {
    __IOM uint32_t TRIG3;                       /*!< (@ 0x00000070) Channel3 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG3_f;
  } ;
  __IM  uint32_t  RESERVED3[3];
  
  union {
    __IOM uint32_t CSR4;                        /*!< (@ 0x00000080) Channel4 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IM  uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
    } CSR4_f;
  } ;
  
  union {
    __IOM uint32_t CNT4;                        /*!< (@ 0x00000084) Channel4 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT4_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR4;                    /*!< (@ 0x00000088) Channel4 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR4_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR4;                    /*!< (@ 0x0000008C) Channel4 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR4_f;
  } ;
  
  union {
    __IOM uint32_t TRIG4;                       /*!< (@ 0x00000090) Channel4 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG4_f;
  } ;
  __IM  uint32_t  RESERVED4[3];
  
  union {
    __IOM uint32_t CSR5;                        /*!< (@ 0x000000A0) Channel5 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IM  uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
    } CSR5_f;
  } ;
  
  union {
    __IOM uint32_t CNT5;                        /*!< (@ 0x000000A4) Channel5 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT5_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR5;                    /*!< (@ 0x000000A8) Channel5 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR5_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR5;                    /*!< (@ 0x000000AC) Channel5 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR5_f;
  } ;
  
  union {
    __IOM uint32_t TRIG5;                       /*!< (@ 0x000000B0) Channel5 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG5_f;
  } ;
} DMA_TypeDef;                                     /*!< Size = 180 (0xb4)                                                         */



/* =========================================================================================================================== */
/* ================                                        DMACHANNEL1                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA Channel 1 (DMACHANNEL1)
  */

typedef struct {                                /*!< (@ 0x40020020) DMACHANNEL1 Structure                                      */
  
  union {
    __IOM uint32_t CSR;                         /*!< (@ 0x00000000) Channel.y control and status register                      */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IM  uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
    } CSR_f;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000004) Channel.y counter register                                 */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR;                     /*!< (@ 0x00000008) Channel.y source address register                          */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR;                     /*!< (@ 0x0000000C) Channel.y destination address register                     */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR_f;
  } ;
  
  union {
    __IOM uint32_t TRIG;                        /*!< (@ 0x00000010) Channel.y trigger register                                 */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG_f;
  } ;
} DMACHANNEL_TypeDef;                              /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc FLASH (FLASH)
  */

typedef struct {                                /*!< (@ 0x40022000) FLASH Structure                                            */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t MODE       : 2;            /*!< [1..0] desc MODE                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t STANDBY    : 1;            /*!< [4..4] desc STANDBY                                                       */
      __IM  uint32_t BUSY       : 1;            /*!< [5..5] desc BUSY                                                          */
      __IM  uint32_t SECURITY   : 2;            /*!< [7..6] desc SECURITY                                                      */
      __IM  uint32_t            : 8;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) Control register2                                          */
    
    struct {
      __IOM uint32_t WAIT       : 3;            /*!< [2..0] desc WAIT                                                          */
      __IOM uint32_t FETCH      : 1;            /*!< [3..3] desc FETCH                                                         */
      __IOM uint32_t CACHE      : 1;            /*!< [4..4] desc CACHE                                                         */
      __IM  uint32_t            : 11;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t PAGELOCK;                    /*!< (@ 0x00000008) Page Write Erase Lock                                      */
    
    struct {
      __IOM uint32_t LOCK0      : 1;            /*!< [0..0] Page0 - 7                                                          */
      __IOM uint32_t LOCK1      : 1;            /*!< [1..1] Page8 - 15                                                         */
      __IOM uint32_t LOCK2      : 1;            /*!< [2..2] Page16 - 23                                                        */
      __IOM uint32_t LOCK3      : 1;            /*!< [3..3] Page24 - 31                                                        */
      __IOM uint32_t LOCK4      : 1;            /*!< [4..4] Page32 - 39                                                        */
      __IOM uint32_t LOCK5      : 1;            /*!< [5..5] Page40 - 47                                                        */
      __IOM uint32_t LOCK6      : 1;            /*!< [6..6] Page48 - 55                                                        */
      __IOM uint32_t LOCK7      : 1;            /*!< [7..7] Page56 - 63                                                        */
      __IOM uint32_t LOCK8      : 1;            /*!< [8..8] Page64 - 71                                                        */
      __IOM uint32_t LOCK9      : 1;            /*!< [9..9] Page72 - 79                                                        */
      __IOM uint32_t LOCK10     : 1;            /*!< [10..10] Page80 - 87                                                      */
      __IOM uint32_t LOCK11     : 1;            /*!< [11..11] Page88 - 95                                                      */
      __IOM uint32_t LOCK12     : 1;            /*!< [12..12] Page96 - 103                                                     */
      __IOM uint32_t LOCK13     : 1;            /*!< [13..13] Page104 - 111                                                    */
      __IOM uint32_t LOCK14     : 1;            /*!< [14..14] Page112 - 119                                                    */
      __IOM uint32_t LOCK15     : 1;            /*!< [15..15] Page120 - 127                                                    */
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } PAGELOCK_f;
  } ;
  __IM  uint32_t  RESERVED[5];
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000020) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PC         : 1;            /*!< [0..0] desc PC                                                            */
      __IOM uint32_t PAGELOCK   : 1;            /*!< [1..1] desc PAGELOCK                                                      */
      __IM  uint32_t            : 2;
      __IOM uint32_t PROG       : 1;            /*!< [4..4] desc PROG                                                          */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000024) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t PC         : 1;            /*!< [0..0] desc PC                                                            */
      __IM  uint32_t PAGELOCK   : 1;            /*!< [1..1] desc PAGELOCK                                                      */
      __IM  uint32_t            : 2;
      __IM  uint32_t PROG       : 1;            /*!< [4..4] desc PROG                                                          */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000028) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t PC         : 1;            /*!< [0..0] desc PC                                                            */
      __IOM uint32_t PAGELOCK   : 1;            /*!< [1..1] desc PAGELOCK                                                      */
      __IM  uint32_t            : 2;
      __IOM uint32_t PROG       : 1;            /*!< [4..4] desc PROG                                                          */
    } ICR_f;
  } ;
} FLASH_TypeDef;                                   /*!< Size = 44 (0x2c)                                                          */



/* =========================================================================================================================== */
/* ================                                           GPIOA                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc GPIOA (GPIOA)
  */

typedef struct {                                /*!< (@ 0x48000000) GPIOA Structure                                            */
  
  union {
    __IOM uint32_t DIR;                         /*!< (@ 0x00000000) desc DIR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } DIR_f;
  } ;
  
  union {
    __IOM uint32_t OPENDRAIN;                   /*!< (@ 0x00000004) desc OPENDRAIN                                             */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } OPENDRAIN_f;
  } ;
  
  union {
    __IOM uint32_t SPEED;                       /*!< (@ 0x00000008) desc SPEED                                                 */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } SPEED_f;
  } ;
  
  union {
    __IOM uint32_t PDR;                         /*!< (@ 0x0000000C) desc PDR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } PDR_f;
  } ;
  
  union {
    __IOM uint32_t PUR;                         /*!< (@ 0x00000010) desc PUR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } PUR_f;
  } ;
  
  union {
    __IOM uint32_t AFRH;                        /*!< (@ 0x00000014) desc AFRH                                                  */
    
    struct {
      __IOM uint32_t AFR8       : 4;            /*!< [3..0] desc AFR8                                                          */
      __IOM uint32_t AFR9       : 4;            /*!< [7..4] desc AFR9                                                          */
      __IOM uint32_t AFR10      : 4;            /*!< [11..8] desc AFR10                                                        */
      __IOM uint32_t AFR11      : 4;            /*!< [15..12] desc AFR11                                                       */
      __IOM uint32_t AFR12      : 4;            /*!< [19..16] desc AFR12                                                       */
      __IOM uint32_t AFR13      : 4;            /*!< [23..20] desc AFR13                                                       */
      __IOM uint32_t AFR14      : 4;            /*!< [27..24] desc AFR14                                                       */
      __IOM uint32_t AFR15      : 4;            /*!< [31..28] desc AFR15                                                       */
    } AFRH_f;
  } ;
  
  union {
    __IOM uint32_t AFRL;                        /*!< (@ 0x00000018) desc AFRL                                                  */
    
    struct {
      __IOM uint32_t AFR0       : 4;            /*!< [3..0] desc AFR0                                                          */
      __IOM uint32_t AFR1       : 4;            /*!< [7..4] desc AFR1                                                          */
      __IOM uint32_t AFR2       : 4;            /*!< [11..8] desc AFR2                                                         */
      __IOM uint32_t AFR3       : 4;            /*!< [15..12] desc AFR3                                                        */
      __IOM uint32_t AFR4       : 4;            /*!< [19..16] desc AFR4                                                        */
      __IOM uint32_t AFR5       : 4;            /*!< [23..20] desc AFR5                                                        */
      __IOM uint32_t AFR6       : 4;            /*!< [27..24] desc AFR6                                                        */
      __IOM uint32_t AFR7       : 4;            /*!< [31..28] desc AFR7                                                        */
    } AFRL_f;
  } ;
  
  union {
    __IOM uint32_t ANALOG;                      /*!< (@ 0x0000001C) desc ANALOG                                                */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ANALOG_f;
  } ;
  
  union {
    __IOM uint32_t DRIVER;                      /*!< (@ 0x00000020) desc DRIVER                                                */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } DRIVER_f;
  } ;
  
  union {
    __IOM uint32_t RISEIE;                      /*!< (@ 0x00000024) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } RISEIE_f;
  } ;
  
  union {
    __IOM uint32_t FALLIE;                      /*!< (@ 0x00000028) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } FALLIE_f;
  } ;
  
  union {
    __IOM uint32_t HIGHIE;                      /*!< (@ 0x0000002C) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } HIGHIE_f;
  } ;
  
  union {
    __IOM uint32_t LOWIE;                       /*!< (@ 0x00000030) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } LOWIE_f;
  } ;
  
  union {
    __IOM uint32_t ISR;                         /*!< (@ 0x00000034) Interrupt status register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000038) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t LOCK;                        /*!< (@ 0x0000003C) desc LOCK                                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
      __OM  uint32_t KEY        : 16;           /*!< [31..16] KEY = 0x5A5A                                                     */
    } LOCK_f;
  } ;
  
  union {
    __IOM uint32_t FILTER;                      /*!< (@ 0x00000040) desc FILTER                                                */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
      __IOM uint32_t FLTCLK     : 3;            /*!< [18..16] desc FLTCLK                                                      */
    } FILTER_f;
  } ;
  __IM  uint32_t  RESERVED[3];
  
  union {
    __IOM uint32_t IDR;                         /*!< (@ 0x00000050) desc IDR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } IDR_f;
  } ;
  
  union {
    union {
      __IOM uint32_t ODR;                       /*!< (@ 0x00000054) desc ODR                                                   */
      
      struct {
        __IOM uint32_t PIN0     : 1;            /*!< [0..0] desc PIN0                                                          */
        __IOM uint32_t PIN1     : 1;            /*!< [1..1] desc PIN1                                                          */
        __IOM uint32_t PIN2     : 1;            /*!< [2..2] desc PIN2                                                          */
        __IOM uint32_t PIN3     : 1;            /*!< [3..3] desc PIN3                                                          */
        __IOM uint32_t PIN4     : 1;            /*!< [4..4] desc PIN4                                                          */
        __IOM uint32_t PIN5     : 1;            /*!< [5..5] desc PIN5                                                          */
        __IOM uint32_t PIN6     : 1;            /*!< [6..6] desc PIN6                                                          */
        __IOM uint32_t PIN7     : 1;            /*!< [7..7] desc PIN7                                                          */
        __IOM uint32_t PIN8     : 1;            /*!< [8..8] desc PIN8                                                          */
        __IOM uint32_t PIN9     : 1;            /*!< [9..9] desc PIN9                                                          */
        __IOM uint32_t PIN10    : 1;            /*!< [10..10] desc PIN10                                                       */
        __IOM uint32_t PIN11    : 1;            /*!< [11..11] desc PIN11                                                       */
        __IOM uint32_t PIN12    : 1;            /*!< [12..12] desc PIN12                                                       */
        __IOM uint32_t PIN13    : 1;            /*!< [13..13] desc PIN13                                                       */
        __IOM uint32_t PIN14    : 1;            /*!< [14..14] desc PIN14                                                       */
        __IOM uint32_t PIN15    : 1;            /*!< [15..15] desc PIN15                                                       */
      } ODR_f;
    } ;
    
    struct {
      union {
        __IOM uint8_t ODRLOWBYTE;               /*!< (@ 0x00000054) desc ODRLOWBYTE                                            */
        
        struct {
          __IOM uint8_t LOWBYTE : 8;            /*!< [7..0] desc LOWBYTE                                                       */
        } ODRLOWBYTE_f;
      } ;
      
      union {
        __IOM uint8_t ODRHIGHBYTE;              /*!< (@ 0x00000055) desc ODRHIGHBYTE                                           */
        
        struct {
          __IOM uint8_t HIGHBYTE : 8;           /*!< [7..0] desc HIGHBYTE                                                      */
        } ODRHIGHBYTE_f;
      } ;
    };
  };
  
  union {
    __IOM uint32_t BRR;                         /*!< (@ 0x00000058) desc BRR                                                   */
    
    struct {
      __IOM uint32_t BRR0       : 1;            /*!< [0..0] desc BRR0                                                          */
      __IOM uint32_t BRR1       : 1;            /*!< [1..1] desc BRR1                                                          */
      __IOM uint32_t BRR2       : 1;            /*!< [2..2] desc BRR2                                                          */
      __IOM uint32_t BRR3       : 1;            /*!< [3..3] desc BRR3                                                          */
      __IOM uint32_t BRR4       : 1;            /*!< [4..4] desc BRR4                                                          */
      __IOM uint32_t BRR5       : 1;            /*!< [5..5] desc BRR5                                                          */
      __IOM uint32_t BRR6       : 1;            /*!< [6..6] desc BRR6                                                          */
      __IOM uint32_t BRR7       : 1;            /*!< [7..7] desc BRR7                                                          */
      __IOM uint32_t BRR8       : 1;            /*!< [8..8] desc BRR8                                                          */
      __IOM uint32_t BRR9       : 1;            /*!< [9..9] desc BRR9                                                          */
      __IOM uint32_t BRR10      : 1;            /*!< [10..10] desc BRR10                                                       */
      __IOM uint32_t BRR11      : 1;            /*!< [11..11] desc BRR11                                                       */
      __IOM uint32_t BRR12      : 1;            /*!< [12..12] desc BRR12                                                       */
      __IOM uint32_t BRR13      : 1;            /*!< [13..13] desc BRR13                                                       */
      __IOM uint32_t BRR14      : 1;            /*!< [14..14] desc BRR14                                                       */
      __IOM uint32_t BRR15      : 1;            /*!< [15..15] desc BRR15                                                       */
    } BRR_f;
  } ;
  
  union {
    __IOM uint32_t BSRR;                        /*!< (@ 0x0000005C) desc BSRR                                                  */
    
    struct {
      __IOM uint32_t BSS0       : 1;            /*!< [0..0] desc BSS0                                                          */
      __IOM uint32_t BSS1       : 1;            /*!< [1..1] desc BSS1                                                          */
      __IOM uint32_t BSS2       : 1;            /*!< [2..2] desc BSS2                                                          */
      __IOM uint32_t BSS3       : 1;            /*!< [3..3] desc BSS3                                                          */
      __IOM uint32_t BSS4       : 1;            /*!< [4..4] desc BSS4                                                          */
      __IOM uint32_t BSS5       : 1;            /*!< [5..5] desc BSS5                                                          */
      __IOM uint32_t BSS6       : 1;            /*!< [6..6] desc BSS6                                                          */
      __IOM uint32_t BSS7       : 1;            /*!< [7..7] desc BSS7                                                          */
      __IOM uint32_t BSS8       : 1;            /*!< [8..8] desc BSS8                                                          */
      __IOM uint32_t BSS9       : 1;            /*!< [9..9] desc BSS9                                                          */
      __IOM uint32_t BSS10      : 1;            /*!< [10..10] desc BSS10                                                       */
      __IOM uint32_t BSS11      : 1;            /*!< [11..11] desc BSS11                                                       */
      __IOM uint32_t BSS12      : 1;            /*!< [12..12] desc BSS12                                                       */
      __IOM uint32_t BSS13      : 1;            /*!< [13..13] desc BSS13                                                       */
      __IOM uint32_t BSS14      : 1;            /*!< [14..14] desc BSS14                                                       */
      __IOM uint32_t BSS15      : 1;            /*!< [15..15] desc BSS15                                                       */
      __IOM uint32_t BRR0       : 1;            /*!< [16..16] desc BRR0                                                        */
      __IOM uint32_t BRR1       : 1;            /*!< [17..17] desc BRR1                                                        */
      __IOM uint32_t BRR2       : 1;            /*!< [18..18] desc BRR2                                                        */
      __IOM uint32_t BRR3       : 1;            /*!< [19..19] desc BRR3                                                        */
      __IOM uint32_t BRR4       : 1;            /*!< [20..20] desc BRR4                                                        */
      __IOM uint32_t BRR5       : 1;            /*!< [21..21] desc BRR5                                                        */
      __IOM uint32_t BRR6       : 1;            /*!< [22..22] desc BRR6                                                        */
      __IOM uint32_t BRR7       : 1;            /*!< [23..23] desc BRR7                                                        */
      __IOM uint32_t BRR8       : 1;            /*!< [24..24] desc BRR8                                                        */
      __IOM uint32_t BRR9       : 1;            /*!< [25..25] desc BRR9                                                        */
      __IOM uint32_t BRR10      : 1;            /*!< [26..26] desc BRR10                                                       */
      __IOM uint32_t BRR11      : 1;            /*!< [27..27] desc BRR11                                                       */
      __IOM uint32_t BRR12      : 1;            /*!< [28..28] desc BRR12                                                       */
      __IOM uint32_t BRR13      : 1;            /*!< [29..29] desc BRR13                                                       */
      __IOM uint32_t BRR14      : 1;            /*!< [30..30] desc BRR14                                                       */
      __IOM uint32_t BRR15      : 1;            /*!< [31..31] desc BRR15                                                       */
    } BSRR_f;
  } ;
  
  union {
    __IOM uint32_t TOG;                         /*!< (@ 0x00000060) desc TOG                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } TOG_f;
  } ;
} GPIO_TypeDef;                                    /*!< Size = 100 (0x64)                                                         */



/* =========================================================================================================================== */
/* ================                                           GPIOC                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc GPIOC (GPIOC)
  */

typedef struct {                                /*!< (@ 0x48000800) GPIOC Structure                                            */
  
  union {
    __IOM uint32_t DIR;                         /*!< (@ 0x00000000) desc DIR                                                   */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } DIR_f;
  } ;
  
  union {
    __IOM uint32_t OPENDRAIN;                   /*!< (@ 0x00000004) desc OPENDRAIN                                             */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } OPENDRAIN_f;
  } ;
  
  union {
    __IOM uint32_t SPEED;                       /*!< (@ 0x00000008) desc SPEED                                                 */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } SPEED_f;
  } ;
  
  union {
    __IOM uint32_t PDR;                         /*!< (@ 0x0000000C) desc PDR                                                   */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } PDR_f;
  } ;
  
  union {
    __IOM uint32_t PUR;                         /*!< (@ 0x00000010) desc PUR                                                   */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } PUR_f;
  } ;
  
  union {
    __IOM uint32_t AFRH;                        /*!< (@ 0x00000014) desc AFRH                                                  */
    
    struct {
      __IM  uint32_t            : 20;
      __IOM uint32_t AFR13      : 4;            /*!< [23..20] desc AFR13                                                       */
      __IOM uint32_t AFR14      : 4;            /*!< [27..24] desc AFR14                                                       */
      __IOM uint32_t AFR15      : 4;            /*!< [31..28] desc AFR15                                                       */
    } AFRH_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t ANALOG;                      /*!< (@ 0x0000001C) desc ANALOG                                                */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ANALOG_f;
  } ;
  
  union {
    __IOM uint32_t DRIVER;                      /*!< (@ 0x00000020) desc DRIVER                                                */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } DRIVER_f;
  } ;
  
  union {
    __IOM uint32_t RISEIE;                      /*!< (@ 0x00000024) Interrupt enable register                                  */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } RISEIE_f;
  } ;
  
  union {
    __IOM uint32_t FALLIE;                      /*!< (@ 0x00000028) Interrupt enable register                                  */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } FALLIE_f;
  } ;
  
  union {
    __IOM uint32_t HIGHIE;                      /*!< (@ 0x0000002C) Interrupt enable register                                  */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } HIGHIE_f;
  } ;
  
  union {
    __IOM uint32_t LOWIE;                       /*!< (@ 0x00000030) Interrupt enable register                                  */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } LOWIE_f;
  } ;
  
  union {
    __IOM uint32_t ISR;                         /*!< (@ 0x00000034) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000038) Interrupt flag clear register                              */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t LOCK;                        /*!< (@ 0x0000003C) desc LOCK                                                  */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
      __OM  uint32_t KEY        : 16;           /*!< [31..16] KEY = 0x5A5A                                                     */
    } LOCK_f;
  } ;
  
  union {
    __IOM uint32_t FILTER;                      /*!< (@ 0x00000040) desc FILTER                                                */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
      __IOM uint32_t FLTCLK     : 3;            /*!< [18..16] desc FLTCLK                                                      */
    } FILTER_f;
  } ;
  __IM  uint32_t  RESERVED1[3];
  
  union {
    __IOM uint32_t IDR;                         /*!< (@ 0x00000050) desc IDR                                                   */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } IDR_f;
  } ;
  
  union {
    union {
      __IOM uint32_t ODR;                       /*!< (@ 0x00000054) desc ODR                                                   */
      
      struct {
        __IM  uint32_t          : 13;
        __IOM uint32_t PIN13    : 1;            /*!< [13..13] desc PIN13                                                       */
        __IOM uint32_t PIN14    : 1;            /*!< [14..14] desc PIN14                                                       */
        __IOM uint32_t PIN15    : 1;            /*!< [15..15] desc PIN15                                                       */
      } ODR_f;
    } ;
    
    struct {
      union {
        __IOM uint8_t ODRLOWBYTE;               /*!< (@ 0x00000054) desc ODRLOWBYTE                                            */
        
        struct {
          __IOM uint8_t LOWBYTE : 8;            /*!< [7..0] desc LOWBYTE                                                       */
        } ODRLOWBYTE_f;
      } ;
      
      union {
        __IOM uint8_t ODRHIGHBYTE;              /*!< (@ 0x00000055) desc ODRHIGHBYTE                                           */
        
        struct {
          __IOM uint8_t HIGHBYTE : 8;           /*!< [7..0] desc HIGHBYTE                                                      */
        } ODRHIGHBYTE_f;
      } ;
    };
  };
  
  union {
    __IOM uint32_t BRR;                         /*!< (@ 0x00000058) desc BRR                                                   */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t BRR13      : 1;            /*!< [13..13] desc BRR13                                                       */
      __IOM uint32_t BRR14      : 1;            /*!< [14..14] desc BRR14                                                       */
      __IOM uint32_t BRR15      : 1;            /*!< [15..15] desc BRR15                                                       */
    } BRR_f;
  } ;
  
  union {
    __IOM uint32_t BSRR;                        /*!< (@ 0x0000005C) desc BSRR                                                  */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t BSS13      : 1;            /*!< [13..13] desc BSS13                                                       */
      __IOM uint32_t BSS14      : 1;            /*!< [14..14] desc BSS14                                                       */
      __IOM uint32_t BSS15      : 1;            /*!< [15..15] desc BSS15                                                       */
      __IM  uint32_t            : 13;
      __IOM uint32_t BRR13      : 1;            /*!< [29..29] desc BRR13                                                       */
      __IOM uint32_t BRR14      : 1;            /*!< [30..30] desc BRR14                                                       */
      __IOM uint32_t BRR15      : 1;            /*!< [31..31] desc BRR15                                                       */
    } BSRR_f;
  } ;
  
  union {
    __IOM uint32_t TOG;                         /*!< (@ 0x00000060) desc TOG                                                   */
    
    struct {
      __IM  uint32_t            : 13;
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } TOG_f;
  } ;
} GPIOC_TypeDef;                                   /*!< Size = 100 (0x64)                                                         */



/* =========================================================================================================================== */
/* ================                                           GPIOF                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc GPIOF (GPIOF)
  */

typedef struct {                                /*!< (@ 0x48001400) GPIOF Structure                                            */
  
  union {
    __IOM uint32_t DIR;                         /*!< (@ 0x00000000) desc DIR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } DIR_f;
  } ;
  
  union {
    __IOM uint32_t OPENDRAIN;                   /*!< (@ 0x00000004) desc OPENDRAIN                                             */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } OPENDRAIN_f;
  } ;
  
  union {
    __IOM uint32_t SPEED;                       /*!< (@ 0x00000008) desc SPEED                                                 */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } SPEED_f;
  } ;
  
  union {
    __IOM uint32_t PDR;                         /*!< (@ 0x0000000C) desc PDR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } PDR_f;
  } ;
  
  union {
    __IOM uint32_t PUR;                         /*!< (@ 0x00000010) desc PUR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } PUR_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t AFRL;                        /*!< (@ 0x00000018) desc AFRL                                                  */
    
    struct {
      __IOM uint32_t AFR0       : 4;            /*!< [3..0] desc AFR0                                                          */
      __IOM uint32_t AFR1       : 4;            /*!< [7..4] desc AFR1                                                          */
      __IM  uint32_t            : 4;
      __IOM uint32_t AFR3       : 4;            /*!< [15..12] desc AFR3                                                        */
      __IM  uint32_t            : 8;
      __IOM uint32_t AFR6       : 4;            /*!< [27..24] desc AFR6                                                        */
      __IOM uint32_t AFR7       : 4;            /*!< [31..28] desc AFR7                                                        */
    } AFRL_f;
  } ;
  
  union {
    __IOM uint32_t ANALOG;                      /*!< (@ 0x0000001C) desc ANALOG                                                */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } ANALOG_f;
  } ;
  
  union {
    __IOM uint32_t DRIVER;                      /*!< (@ 0x00000020) desc DRIVER                                                */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } DRIVER_f;
  } ;
  
  union {
    __IOM uint32_t RISEIE;                      /*!< (@ 0x00000024) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } RISEIE_f;
  } ;
  
  union {
    __IOM uint32_t FALLIE;                      /*!< (@ 0x00000028) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } FALLIE_f;
  } ;
  
  union {
    __IOM uint32_t HIGHIE;                      /*!< (@ 0x0000002C) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } HIGHIE_f;
  } ;
  
  union {
    __IOM uint32_t LOWIE;                       /*!< (@ 0x00000030) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } LOWIE_f;
  } ;
  
  union {
    __IOM uint32_t ISR;                         /*!< (@ 0x00000034) Interrupt status register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000038) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t LOCK;                        /*!< (@ 0x0000003C) desc LOCK                                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IM  uint32_t            : 8;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] KEY = 0x5A5A                                                     */
    } LOCK_f;
  } ;
  
  union {
    __IOM uint32_t FILTER;                      /*!< (@ 0x00000040) desc FILTER                                                */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IM  uint32_t            : 8;
      __IOM uint32_t FLTCLK     : 3;            /*!< [18..16] desc FLTCLK                                                      */
    } FILTER_f;
  } ;
  __IM  uint32_t  RESERVED1[3];
  
  union {
    __IOM uint32_t IDR;                         /*!< (@ 0x00000050) desc IDR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } IDR_f;
  } ;
  
  union {
    union {
      __IOM uint32_t ODR;                       /*!< (@ 0x00000054) desc ODR                                                   */
      
      struct {
        __IOM uint32_t PIN0     : 1;            /*!< [0..0] desc PIN0                                                          */
        __IOM uint32_t PIN1     : 1;            /*!< [1..1] desc PIN1                                                          */
        __IM  uint32_t          : 1;
        __IOM uint32_t PIN3     : 1;            /*!< [3..3] desc PIN3                                                          */
        __IM  uint32_t          : 2;
        __IOM uint32_t PIN6     : 1;            /*!< [6..6] desc PIN6                                                          */
        __IOM uint32_t PIN7     : 1;            /*!< [7..7] desc PIN7                                                          */
      } ODR_f;
    } ;
    
    union {
      __IOM uint8_t ODRLOWBYTE;                 /*!< (@ 0x00000054) desc ODRLOWBYTE                                            */
      
      struct {
        __IOM uint8_t LOWBYTE   : 8;            /*!< [7..0] desc LOWBYTE                                                       */
      } ODRLOWBYTE_f;
    } ;
  };
  
  union {
    __IOM uint32_t BRR;                         /*!< (@ 0x00000058) desc BRR                                                   */
    
    struct {
      __IOM uint32_t BRR0       : 1;            /*!< [0..0] desc BRR0                                                          */
      __IOM uint32_t BRR1       : 1;            /*!< [1..1] desc BRR1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t BRR3       : 1;            /*!< [3..3] desc BRR3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t BRR6       : 1;            /*!< [6..6] desc BRR6                                                          */
      __IOM uint32_t BRR7       : 1;            /*!< [7..7] desc BRR7                                                          */
    } BRR_f;
  } ;
  
  union {
    __IOM uint32_t BSRR;                        /*!< (@ 0x0000005C) desc BSRR                                                  */
    
    struct {
      __IOM uint32_t BSS0       : 1;            /*!< [0..0] desc BSS0                                                          */
      __IOM uint32_t BSS1       : 1;            /*!< [1..1] desc BSS1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t BSS3       : 1;            /*!< [3..3] desc BSS3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t BSS6       : 1;            /*!< [6..6] desc BSS6                                                          */
      __IOM uint32_t BSS7       : 1;            /*!< [7..7] desc BSS7                                                          */
    } BSRR_f;
  } ;
  
  union {
    __IOM uint32_t TOG;                         /*!< (@ 0x00000060) desc TOG                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
    } TOG_f;
  } ;
} GPIOF_TypeDef;                                   /*!< Size = 100 (0x64)                                                         */



/* =========================================================================================================================== */
/* ================                                           GTIM1                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General Timer 1 (GTIM1)
  */

typedef struct {                                /*!< (@ 0x40000400) GTIM1 Structure                                            */
  __IM  uint32_t  RESERVED[192];
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x00000300) Auto Reload Register                                       */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000304) Counter Register                                           */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
    } CNT_f;
  } ;
  
  union {
    __IOM uint32_t CMMR;                        /*!< (@ 0x00000308) Capture compare control Register                           */
    
    struct {
      __IOM uint32_t CC1M       : 4;            /*!< [3..0] desc CC1M                                                          */
      __IOM uint32_t CC2M       : 4;            /*!< [7..4] desc CC2M                                                          */
      __IOM uint32_t CC3M       : 4;            /*!< [11..8] desc CC3M                                                         */
      __IOM uint32_t CC4M       : 4;            /*!< [15..12] desc CC4M                                                        */
    } CMMR_f;
  } ;
  
  union {
    __IOM uint32_t ETR;                         /*!< (@ 0x0000030C) ETR Control register                                       */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t ETRFLT     : 3;            /*!< [6..4] desc ETRFLT                                                        */
    } ETR_f;
  } ;
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000310) Control register0                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t MODE       : 2;            /*!< [2..1] desc MODE                                                          */
      __IOM uint32_t TRS        : 1;            /*!< [3..3] desc TRS                                                           */
      __IOM uint32_t POL        : 1;            /*!< [4..4] desc POL                                                           */
      __IOM uint32_t ONESHOT    : 1;            /*!< [5..5] desc ONESHOT                                                       */
      __IOM uint32_t TOGEN      : 1;            /*!< [6..6] desc TOGEN                                                         */
      __IOM uint32_t PRS        : 4;            /*!< [10..7] desc PRS                                                          */
      __IM  uint32_t PRSSTATUS  : 4;            /*!< [14..11] desc PRSSTATUS                                                   */
      __IOM uint32_t ENCMODE    : 2;            /*!< [16..15] desc ENCMODE                                                     */
      __IOM uint32_t ENCRESET   : 2;            /*!< [18..17] desc ENCRESET                                                    */
      __IOM uint32_t ENCRELOAD  : 2;            /*!< [20..19] desc ENCRELOAD                                                   */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000314) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t OV         : 1;            /*!< [0..0] desc OV                                                            */
      __IOM uint32_t TI         : 1;            /*!< [1..1] desc TI                                                            */
      __IOM uint32_t UD         : 1;            /*!< [2..2] desc UD                                                            */
      __IOM uint32_t CC1        : 1;            /*!< [3..3] desc CC1                                                           */
      __IOM uint32_t CC2        : 1;            /*!< [4..4] desc CC2                                                           */
      __IOM uint32_t CC3        : 1;            /*!< [5..5] desc CC3                                                           */
      __IOM uint32_t CC4        : 1;            /*!< [6..6] desc CC4                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t DIRCHANGE  : 1;            /*!< [9..9] desc DIRCHANGE                                                     */
    } IER_f;
  } ;
  
  union {
    __IOM uint32_t ISR;                         /*!< (@ 0x00000318) Interrupt status register                                  */
    
    struct {
      __IOM uint32_t OV         : 1;            /*!< [0..0] desc OV                                                            */
      __IOM uint32_t TI         : 1;            /*!< [1..1] desc TI                                                            */
      __IOM uint32_t UD         : 1;            /*!< [2..2] desc UD                                                            */
      __IM  uint32_t CC1        : 1;            /*!< [3..3] desc CC1                                                           */
      __IM  uint32_t CC2        : 1;            /*!< [4..4] desc CC2                                                           */
      __IM  uint32_t CC3        : 1;            /*!< [5..5] desc CC3                                                           */
      __IM  uint32_t CC4        : 1;            /*!< [6..6] desc CC4                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t DIRCHANGE  : 1;            /*!< [9..9] desc DIRCHANGE                                                     */
      __IM  uint32_t DIR        : 1;            /*!< [10..10] desc DIR                                                         */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x0000031C) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t OV         : 1;            /*!< [0..0] desc OV                                                            */
      __IOM uint32_t TI         : 1;            /*!< [1..1] desc TI                                                            */
      __IOM uint32_t UD         : 1;            /*!< [2..2] desc UD                                                            */
      __IOM uint32_t CC1        : 1;            /*!< [3..3] desc CC1                                                           */
      __IOM uint32_t CC2        : 1;            /*!< [4..4] desc CC2                                                           */
      __IOM uint32_t CC3        : 1;            /*!< [5..5] desc CC3                                                           */
      __IOM uint32_t CC4        : 1;            /*!< [6..6] desc CC4                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t DIRCHANGE  : 1;            /*!< [9..9] desc DIRCHANGE                                                     */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t CCR1;                        /*!< (@ 0x00000320) capture compare register                                   */
    
    struct {
      __IOM uint32_t CCR        : 16;           /*!< [15..0] desc CCR                                                          */
    } CCR1_f;
  } ;
  
  union {
    __IOM uint32_t CCR2;                        /*!< (@ 0x00000324) capture compare register                                   */
    
    struct {
      __IOM uint32_t CCR        : 16;           /*!< [15..0] desc CCR                                                          */
    } CCR2_f;
  } ;
  
  union {
    __IOM uint32_t CCR3;                        /*!< (@ 0x00000328) capture compare register                                   */
    
    struct {
      __IOM uint32_t CCR        : 16;           /*!< [15..0] desc CCR                                                          */
    } CCR3_f;
  } ;
  
  union {
    __IOM uint32_t CCR4;                        /*!< (@ 0x0000032C) capture compare register                                   */
    
    struct {
      __IOM uint32_t CCR        : 16;           /*!< [15..0] desc CCR                                                          */
    } CCR4_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000330) Control register1                                          */
    
    struct {
      __IOM uint32_t CH1FLT     : 3;            /*!< [2..0] desc CH1FLT                                                        */
      __IOM uint32_t CH1POL     : 1;            /*!< [3..3] desc CH1POL                                                        */
      __IOM uint32_t CH2FLT     : 3;            /*!< [6..4] desc CH2FLT                                                        */
      __IOM uint32_t CH2POL     : 1;            /*!< [7..7] desc CH2POL                                                        */
      __IOM uint32_t CH3FLT     : 3;            /*!< [10..8] desc CH3FLT                                                       */
      __IOM uint32_t CH3POL     : 1;            /*!< [11..11] desc CH3POL                                                      */
      __IOM uint32_t CH4FLT     : 3;            /*!< [14..12] desc CH4FLT                                                      */
      __IOM uint32_t CH4POL     : 1;            /*!< [15..15] desc CH4POL                                                      */
    } CR1_f;
  } ;
  __IM  uint32_t  RESERVED1[3];
  
  union {
    __IOM uint32_t DMA;                         /*!< (@ 0x00000340) DMA Control register                                       */
    
    struct {
      __IOM uint32_t OV         : 1;            /*!< [0..0] desc OV                                                            */
      __IOM uint32_t TRS        : 1;            /*!< [1..1] desc TRS                                                           */
      __IOM uint32_t CC1        : 1;            /*!< [2..2] desc CC1                                                           */
      __IOM uint32_t CC2        : 1;            /*!< [3..3] desc CC2                                                           */
      __IOM uint32_t CC3        : 1;            /*!< [4..4] desc CC3                                                           */
      __IOM uint32_t CC4        : 1;            /*!< [5..5] desc CC4                                                           */
    } DMA_f;
  } ;
} GTIM_TypeDef;                                    /*!< Size = 836 (0x344)                                                        */



/* =========================================================================================================================== */
/* ================                                           I2C1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc I2C1 (I2C1)
  */

typedef struct {                                /*!< (@ 0x40005400) I2C1 Structure                                             */
  
  union {
    __IOM uint32_t BRREN;                       /*!< (@ 0x00000000) desc BRREN                                                 */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
    } BRREN_f;
  } ;
  
  union {
    __IOM uint32_t BRR;                         /*!< (@ 0x00000004) desc BRR                                                   */
    
    struct {
      __IOM uint32_t BRR        : 8;            /*!< [7..0] fSCL = fPCLK / 8 / (BRR+1)                                         */
    } BRR_f;
  } ;
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000008) Control register                                           */
    
    struct {
      __IOM uint32_t FLT        : 1;            /*!< [0..0] desc FLT                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t AA         : 1;            /*!< [2..2] desc AA                                                            */
      __IOM uint32_t SI         : 1;            /*!< [3..3] desc SI                                                            */
      __IOM uint32_t STO        : 1;            /*!< [4..4] desc STO                                                           */
      __IOM uint32_t STA        : 1;            /*!< [5..5] desc STA                                                           */
      __IOM uint32_t EN         : 1;            /*!< [6..6] desc EN                                                            */
    } CR_f;
  } ;
  
  union {
    __IOM uint32_t DR;                          /*!< (@ 0x0000000C) Data register                                              */
    
    struct {
      __IOM uint32_t DR         : 8;            /*!< [7..0] desc DR                                                            */
    } DR_f;
  } ;
  
  union {
    __IOM uint32_t ADDR0;                       /*!< (@ 0x00000010) Slave Addrress0                                            */
    
    struct {
      __IOM uint32_t GC         : 1;            /*!< [0..0] desc GC                                                            */
      __IOM uint32_t ADDR0      : 7;            /*!< [7..1] desc ADDR0                                                         */
    } ADDR0_f;
  } ;
  
  union {
    __IM  uint32_t STAT;                        /*!< (@ 0x00000014) Status register                                            */
    
    struct {
      __IM  uint32_t STAT       : 8;            /*!< [7..0] desc STAT                                                          */
    } STAT_f;
  } ;
  __IM  uint32_t  RESERVED[2];
  
  union {
    __IOM uint32_t ADDR1;                       /*!< (@ 0x00000020) Slave Addrress1                                            */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t ADDR1      : 7;            /*!< [7..1] desc ADDR1                                                         */
    } ADDR1_f;
  } ;
  
  union {
    __IOM uint32_t ADDR2;                       /*!< (@ 0x00000024) Slave Addrress2                                            */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t ADDR2      : 7;            /*!< [7..1] desc ADDR2                                                         */
    } ADDR2_f;
  } ;
  
  union {
    __IM  uint32_t MATCH;                       /*!< (@ 0x00000028) Slave Addrress match flag                                  */
    
    struct {
      __IM  uint32_t ADDR0      : 1;            /*!< [0..0] desc ADDR0                                                         */
      __IM  uint32_t ADDR1      : 1;            /*!< [1..1] desc ADDR1                                                         */
      __IM  uint32_t ADDR2      : 1;            /*!< [2..2] desc ADDR2                                                         */
    } MATCH_f;
  } ;
} I2C_TypeDef;                                     /*!< Size = 44 (0x2c)                                                          */



/* =========================================================================================================================== */
/* ================                                           IWDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc IWDT (IWDT)
  */

typedef struct {                                /*!< (@ 0x40003000) IWDT Structure                                             */
  
  union {
    __OM  uint32_t KR;                          /*!< (@ 0x00000000) Key register                                               */
    
    struct {
      __OM  uint32_t KR         : 16;           /*!< [15..0] desc KR                                                           */
    } KR_f;
  } ;
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000004) Control register                                           */
    
    struct {
      __IOM uint32_t PRS        : 3;            /*!< [2..0] desc PRS                                                           */
      __IOM uint32_t ACTION     : 1;            /*!< [3..3] desc ACTION                                                        */
      __IOM uint32_t IE         : 1;            /*!< [4..4] desc IE                                                            */
      __IOM uint32_t PAUSE      : 1;            /*!< [5..5] desc PAUSE                                                         */
    } CR_f;
  } ;
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x00000008) Auto reload register                                       */
    
    struct {
      __IOM uint32_t ARR        : 12;           /*!< [11..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x0000000C) Status register                                            */
    
    struct {
      __IM  uint32_t CRF        : 1;            /*!< [0..0] desc CRF                                                           */
      __IM  uint32_t ARRF       : 1;            /*!< [1..1] desc ARRF                                                          */
      __IM  uint32_t WINRF      : 1;            /*!< [2..2] desc WINRF                                                         */
      __IOM uint32_t OV         : 1;            /*!< [3..3] desc OV                                                            */
      __IM  uint32_t RUN        : 1;            /*!< [4..4] desc RUN                                                           */
      __IM  uint32_t RELOAD     : 1;            /*!< [5..5] desc RELOAD                                                        */
    } SR_f;
  } ;
  
  union {
    __IOM uint32_t WINR;                        /*!< (@ 0x00000010) Window register                                            */
    
    struct {
      __IOM uint32_t WINR       : 12;           /*!< [11..0] desc WINR                                                         */
    } WINR_f;
  } ;
  __IM  uint32_t  RESERVED[4];
  
  union {
    __IM  uint32_t CNT;                         /*!< (@ 0x00000024) counter                                                    */
    
    struct {
      __IM  uint32_t CNT        : 12;           /*!< [11..0] desc CNT                                                          */
    } CNT_f;
  } ;
} IWDT_TypeDef;                                    /*!< Size = 40 (0x28)                                                          */



/* =========================================================================================================================== */
/* ================                                            LVD                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc LVD (LVD)
  */

typedef struct {                                /*!< (@ 0x40012A80) LVD Structure                                              */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) Control register0                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t ACTION     : 1;            /*!< [1..1] desc ACTION                                                        */
      __IOM uint32_t SOURCE     : 2;            /*!< [3..2] desc SOURCE                                                        */
      __IOM uint32_t VTH        : 4;            /*!< [7..4] desc VTH                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t IE         : 1;            /*!< [9..9] desc IE                                                            */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) Control register1                                          */
    
    struct {
      __IOM uint32_t FLTEN      : 1;            /*!< [0..0] desc FLTEN                                                         */
      __IOM uint32_t FLTTIME    : 3;            /*!< [3..1] desc FLTTIME                                                       */
      __IOM uint32_t FLTCLK     : 1;            /*!< [4..4] desc FLTCLK                                                        */
      __IOM uint32_t RISE       : 1;            /*!< [5..5] desc RISE                                                          */
      __IOM uint32_t FALL       : 1;            /*!< [6..6] desc FALL                                                          */
      __IOM uint32_t LEVEL      : 1;            /*!< [7..7] desc LEVEL                                                         */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x00000008) status register                                            */
    
    struct {
      __IOM uint32_t INTF       : 1;            /*!< [0..0] desc INTF                                                          */
      __IM  uint32_t FLTV       : 1;            /*!< [1..1] desc FLTV                                                          */
    } SR_f;
  } ;
} LVD_TypeDef;                                     /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                            RAM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc RAM (RAM)
  */

typedef struct {                                /*!< (@ 0x40022400) RAM Structure                                              */
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000000) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t PARITY     : 1;            /*!< [1..1] desc PARITY                                                        */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ADDR;                        /*!< (@ 0x00000004) Parity check error addr register                           */
    
    struct {
      __IM  uint32_t ADDR       : 32;           /*!< [31..0] desc ADDR                                                         */
    } ADDR_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000008) Interrupt flag register                                    */
    
    struct {
      __IM  uint32_t PARITY     : 1;            /*!< [0..0] desc PARITY                                                        */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x0000000C) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t PARITY     : 1;            /*!< [0..0] desc PARITY                                                        */
    } ICR_f;
  } ;
} RAM_TypeDef;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc RTC (RTC)
  */

typedef struct {                                /*!< (@ 0x40002800) RTC Structure                                              */
  
  union {
    __OM  uint32_t KEY;                         /*!< (@ 0x00000000) desc KEY                                                   */
    
    struct {
      __OM  uint32_t KEY        : 8;            /*!< [7..0] Key = 0xCA - 0x53                                                  */
    } KEY_f;
  } ;
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000004) Control register0                                          */
    
    struct {
      __IOM uint32_t INTERVAL   : 3;            /*!< [2..0] desc INTERVAL                                                      */
      __IOM uint32_t H24        : 1;            /*!< [3..3] desc H24                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t RTC1HZ     : 2;            /*!< [6..5] desc RTC1HZ                                                        */
      __IOM uint32_t START      : 1;            /*!< [7..7] desc START                                                         */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000008) Control register1                                          */
    
    struct {
      __IOM uint32_t ACCESS     : 1;            /*!< [0..0] desc ACCESS                                                        */
      __IM  uint32_t WINDOW     : 1;            /*!< [1..1] desc WINDOW                                                        */
      __IM  uint32_t            : 6;
      __IOM uint32_t SOURCE     : 3;            /*!< [10..8] desc SOURCE                                                       */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x0000000C) Control register2                                          */
    
    struct {
      __IOM uint32_t AWTSRC     : 3;            /*!< [2..0] desc AWTSRC                                                        */
      __IOM uint32_t TAMPEDGE   : 1;            /*!< [3..3] desc TAMPEDGE                                                      */
      __IOM uint32_t RTCOUT     : 2;            /*!< [5..4] desc RTCOUT                                                        */
      __IOM uint32_t TAMPEN     : 1;            /*!< [6..6] desc TAMPEN                                                        */
      __IOM uint32_t AWTEN      : 1;            /*!< [7..7] desc AWTEN                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t ALARMAEN   : 1;            /*!< [9..9] desc ALARMAEN                                                      */
      __IOM uint32_t ALARMBEN   : 1;            /*!< [10..10] desc ALARMBEN                                                    */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t COMPEN;                      /*!< (@ 0x00000010) Compen register                                            */
    
    struct {
      __IOM uint32_t COMP       : 12;           /*!< [11..0] desc COMP                                                         */
      __IOM uint32_t STEP       : 2;            /*!< [13..12] desc STEP                                                        */
      __IOM uint32_t SIGN       : 1;            /*!< [14..14] desc SIGN                                                        */
      __IOM uint32_t EN         : 1;            /*!< [15..15] desc EN                                                          */
      __IOM uint32_t FREQ       : 4;            /*!< [19..16] desc FREQ                                                        */
    } COMPEN_f;
  } ;
  
  union {
    __IOM uint32_t DATE;                        /*!< (@ 0x00000014) Time.Second register                                       */
    
    struct {
      __IOM uint32_t DAY        : 8;            /*!< [7..0] desc DAY                                                           */
      __IOM uint32_t MONTH      : 8;            /*!< [15..8] desc MONTH                                                        */
      __IOM uint32_t YEAR       : 8;            /*!< [23..16] desc YEAR                                                        */
      __IOM uint32_t WEEK       : 3;            /*!< [26..24] desc WEEK                                                        */
    } DATE_f;
  } ;
  
  union {
    __IOM uint32_t TIME;                        /*!< (@ 0x00000018) Time.Second register                                       */
    
    struct {
      __IOM uint32_t SECOND     : 7;            /*!< [6..0] desc SECOND                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t MINUTE     : 7;            /*!< [14..8] desc MINUTE                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t HOUR       : 6;            /*!< [21..16] desc HOUR                                                        */
    } TIME_f;
  } ;
  
  union {
    __IOM uint32_t ALARMA;                      /*!< (@ 0x0000001C) Alarm - A                                                  */
    
    struct {
      __IOM uint32_t SECOND     : 7;            /*!< [6..0] desc SECOND                                                        */
      __IOM uint32_t SECONDMASK : 1;            /*!< [7..7] desc SECONDMASK                                                    */
      __IOM uint32_t MINUTE     : 7;            /*!< [14..8] desc MINUTE                                                       */
      __IOM uint32_t MINUTEMASK : 1;            /*!< [15..15] desc MINUTEMASK                                                  */
      __IOM uint32_t HOUR       : 6;            /*!< [21..16] desc HOUR                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t HOURMASK   : 1;            /*!< [23..23] desc HOURMASK                                                    */
      __IOM uint32_t WEEK       : 7;            /*!< [30..24] desc WEEK                                                        */
    } ALARMA_f;
  } ;
  
  union {
    __IOM uint32_t ALARMB;                      /*!< (@ 0x00000020) Alarm - B                                                  */
    
    struct {
      __IOM uint32_t SECOND     : 7;            /*!< [6..0] desc SECOND                                                        */
      __IOM uint32_t SECONDMASK : 1;            /*!< [7..7] desc SECONDMASK                                                    */
      __IOM uint32_t MINUTE     : 7;            /*!< [14..8] desc MINUTE                                                       */
      __IOM uint32_t MINUTEMASK : 1;            /*!< [15..15] desc MINUTEMASK                                                  */
      __IOM uint32_t HOUR       : 6;            /*!< [21..16] desc HOUR                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t HOURMASK   : 1;            /*!< [23..23] desc HOURMASK                                                    */
      __IOM uint32_t WEEK       : 7;            /*!< [30..24] desc WEEK                                                        */
    } ALARMB_f;
  } ;
  
  union {
    __IOM uint32_t TAMPDATE;                    /*!< (@ 0x00000024) desc TAMPDATE                                              */
    
    struct {
      __IOM uint32_t DAY        : 6;            /*!< [5..0] desc DAY                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t MONTH      : 5;            /*!< [12..8] desc MONTH                                                        */
      __IOM uint32_t WEEK       : 3;            /*!< [15..13] desc WEEK                                                        */
    } TAMPDATE_f;
  } ;
  
  union {
    __IOM uint32_t TAMPTIME;                    /*!< (@ 0x00000028) desc TAMPTIME                                              */
    
    struct {
      __IOM uint32_t SECOND     : 7;            /*!< [6..0] desc SECOND                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t MINUTE     : 7;            /*!< [14..8] desc MINUTE                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t HOUR       : 6;            /*!< [21..16] desc HOUR                                                        */
    } TAMPTIME_f;
  } ;
  
  union {
    __IOM uint32_t AWTARR;                      /*!< (@ 0x0000002C) Auto Wakeup Timer Auto Reload Register                     */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } AWTARR_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000030) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t ALARMA     : 1;            /*!< [0..0] desc ALARMA                                                        */
      __IOM uint32_t ALARMB     : 1;            /*!< [1..1] desc ALARMB                                                        */
      __IOM uint32_t AWTIMER    : 1;            /*!< [2..2] desc AWTIMER                                                       */
      __IOM uint32_t TAMP       : 1;            /*!< [3..3] desc TAMP                                                          */
      __IOM uint32_t TAMPOV     : 1;            /*!< [4..4] desc TAMPOV                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t INTERVAL   : 1;            /*!< [6..6] desc INTERVAL                                                      */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000034) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t ALARMA     : 1;            /*!< [0..0] desc ALARMA                                                        */
      __IM  uint32_t ALARMB     : 1;            /*!< [1..1] desc ALARMB                                                        */
      __IM  uint32_t AWTIMER    : 1;            /*!< [2..2] desc AWTIMER                                                       */
      __IM  uint32_t TAMP       : 1;            /*!< [3..3] desc TAMP                                                          */
      __IM  uint32_t TAMPOV     : 1;            /*!< [4..4] desc TAMPOV                                                        */
      __IM  uint32_t            : 1;
      __IM  uint32_t INTERVAL   : 1;            /*!< [6..6] desc INTERVAL                                                      */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000038) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t ALARMA     : 1;            /*!< [0..0] desc ALARMA                                                        */
      __IOM uint32_t ALARMB     : 1;            /*!< [1..1] desc ALARMB                                                        */
      __IOM uint32_t AWTIMER    : 1;            /*!< [2..2] desc AWTIMER                                                       */
      __IOM uint32_t TAMP       : 1;            /*!< [3..3] desc TAMP                                                          */
      __IOM uint32_t TAMPOV     : 1;            /*!< [4..4] desc TAMPOV                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t INTERVAL   : 1;            /*!< [6..6] desc INTERVAL                                                      */
    } ICR_f;
  } ;
} RTC_TypeDef;                                     /*!< Size = 60 (0x3c)                                                          */



/* =========================================================================================================================== */
/* ================                                           SPI1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc SPI1 (SPI1)
  */

typedef struct {                                /*!< (@ 0x40013000) SPI1 Structure                                             */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t CPHA       : 1;            /*!< [0..0] desc CPHA                                                          */
      __IOM uint32_t CPOL       : 1;            /*!< [1..1] desc CPOL                                                          */
      __IOM uint32_t MSTR       : 1;            /*!< [2..2] desc MSTR                                                          */
      __IOM uint32_t BR         : 3;            /*!< [5..3] desc BR                                                            */
      __IOM uint32_t EN         : 1;            /*!< [6..6] desc EN                                                            */
      __IOM uint32_t LSBF       : 1;            /*!< [7..7] desc LSBF                                                          */
      __IOM uint32_t SMP        : 1;            /*!< [8..8] desc SMP                                                           */
      __IOM uint32_t SSM        : 1;            /*!< [9..9] desc SSM                                                           */
      __IOM uint32_t WIDTH      : 4;            /*!< [13..10] desc WIDTH                                                       */
      __IOM uint32_t MODE       : 2;            /*!< [15..14] desc MODE                                                        */
      __IOM uint32_t DMARX      : 1;            /*!< [16..16] desc DMARX                                                       */
      __IOM uint32_t DMATX      : 1;            /*!< [17..17] desc DMATX                                                       */
      __IOM uint32_t MISOHD     : 1;            /*!< [18..18] desc MISOHD                                                      */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000004) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IOM uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IOM uint32_t SSF        : 1;            /*!< [2..2] desc SSF                                                           */
      __IOM uint32_t SSR        : 1;            /*!< [3..3] desc SSR                                                           */
      __IOM uint32_t UD         : 1;            /*!< [4..4] desc UD                                                            */
      __IOM uint32_t OV         : 1;            /*!< [5..5] desc OV                                                            */
      __IOM uint32_t SSERR      : 1;            /*!< [6..6] desc SSERR                                                         */
      __IOM uint32_t MODF       : 1;            /*!< [7..7] desc MODF                                                          */
    } IER_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000008) Control register2                                          */
    
    struct {
      __IOM uint32_t HDOE       : 1;            /*!< [0..0] desc HDOE                                                          */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t SSI;                         /*!< (@ 0x0000000C) Slave slect register                                       */
    
    struct {
      __IOM uint32_t SSI        : 1;            /*!< [0..0] desc SSI                                                           */
    } SSI_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000010) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IM  uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IM  uint32_t SSF        : 1;            /*!< [2..2] desc SSF                                                           */
      __IM  uint32_t SSR        : 1;            /*!< [3..3] desc SSR                                                           */
      __IM  uint32_t UD         : 1;            /*!< [4..4] desc UD                                                            */
      __IM  uint32_t OV         : 1;            /*!< [5..5] desc OV                                                            */
      __IM  uint32_t SSERR      : 1;            /*!< [6..6] desc SSERR                                                         */
      __IM  uint32_t MODF       : 1;            /*!< [7..7] desc MODF                                                          */
      __IM  uint32_t BUSY       : 1;            /*!< [8..8] desc BUSY                                                          */
      __IM  uint32_t SSLVL      : 1;            /*!< [9..9] desc SSLVL                                                         */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000014) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t FLUSH      : 1;            /*!< [0..0] desc FLUSH                                                         */
      __IOM uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IOM uint32_t SSF        : 1;            /*!< [2..2] desc SSF                                                           */
      __IOM uint32_t SSR        : 1;            /*!< [3..3] desc SSR                                                           */
      __IOM uint32_t UD         : 1;            /*!< [4..4] desc UD                                                            */
      __IOM uint32_t OV         : 1;            /*!< [5..5] desc OV                                                            */
      __IOM uint32_t SSERR      : 1;            /*!< [6..6] desc SSERR                                                         */
      __IOM uint32_t MODF       : 1;            /*!< [7..7] desc MODF                                                          */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t DR;                          /*!< (@ 0x00000018) Data register                                              */
    
    struct {
      __IOM uint32_t DR         : 16;           /*!< [15..0] desc DR                                                           */
    } DR_f;
  } ;
} SPI_TypeDef;                                     /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                          SYSCTRL                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief System Ctrl (SYSCTRL)
  */

typedef struct {                                /*!< (@ 0x40010000) SYSCTRL Structure                                          */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) Control Reg0                                               */
    
    struct {
      __IOM uint32_t SYSCLK     : 3;            /*!< [2..0] desc SYSCLK                                                        */
      __IOM uint32_t PCLKPRS    : 2;            /*!< [4..3] desc PCLKPRS                                                       */
      __IOM uint32_t HCLKPRS    : 3;            /*!< [7..5] desc HCLKPRS                                                       */
      __IM  uint32_t            : 8;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) Control Reg1                                               */
    
    struct {
      __IOM uint32_t HSIEN      : 1;            /*!< [0..0] desc HSIEN                                                         */
      __IOM uint32_t HSEEN      : 1;            /*!< [1..1] desc HSEEN                                                         */
      __IOM uint32_t PLLEN      : 1;            /*!< [2..2] desc PLLEN                                                         */
      __IOM uint32_t LSIEN      : 1;            /*!< [3..3] desc LSIEN                                                         */
      __IOM uint32_t LSEEN      : 1;            /*!< [4..4] desc LSEEN                                                         */
      __IOM uint32_t LSELOCK    : 1;            /*!< [5..5] desc LSELOCK                                                       */
      __IOM uint32_t LSECCS     : 1;            /*!< [6..6] desc LSECCS                                                        */
      __IOM uint32_t HSECCS     : 1;            /*!< [7..7] desc HSECCS                                                        */
      __IOM uint32_t CLKCCS     : 1;            /*!< [8..8] desc CLKCCS                                                        */
      __IM  uint32_t            : 7;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000008) Control Reg2                                               */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t SWDIO      : 1;            /*!< [1..1] desc SWDIO                                                         */
      __IOM uint32_t LOCKUP     : 1;            /*!< [2..2] desc LOCKUP                                                        */
      __IOM uint32_t WAKEUPCLK  : 1;            /*!< [3..3] desc WAKEUPCLK                                                     */
      __IM  uint32_t            : 12;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x0000000C) Interupt Enable Reg                                        */
    
    struct {
      __IOM uint32_t HSIRDY     : 1;            /*!< [0..0] desc HSIRDY                                                        */
      __IOM uint32_t HSERDY     : 1;            /*!< [1..1] desc HSERDY                                                        */
      __IOM uint32_t PLLRDY     : 1;            /*!< [2..2] desc PLLRDY                                                        */
      __IOM uint32_t LSIRDY     : 1;            /*!< [3..3] desc LSIRDY                                                        */
      __IOM uint32_t LSERDY     : 1;            /*!< [4..4] desc LSERDY                                                        */
      __IOM uint32_t LSEFAIL    : 1;            /*!< [5..5] desc LSEFAIL                                                       */
      __IOM uint32_t HSEFAIL    : 1;            /*!< [6..6] desc HSEFAIL                                                       */
      __IOM uint32_t LSEFAULT   : 1;            /*!< [7..7] desc LSEFAULT                                                      */
      __IOM uint32_t HSEFAULT   : 1;            /*!< [8..8] desc HSEFAULT                                                      */
      __IM  uint32_t            : 7;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000010) Interupt Status Reg                                        */
    
    struct {
      __IM  uint32_t HSIRDY     : 1;            /*!< [0..0] desc HSIRDY                                                        */
      __IM  uint32_t HSERDY     : 1;            /*!< [1..1] desc HSERDY                                                        */
      __IM  uint32_t PLLRDY     : 1;            /*!< [2..2] desc PLLRDY                                                        */
      __IM  uint32_t LSIRDY     : 1;            /*!< [3..3] desc LSIRDY                                                        */
      __IM  uint32_t LSERDY     : 1;            /*!< [4..4] desc LSERDY                                                        */
      __IM  uint32_t LSEFAIL    : 1;            /*!< [5..5] desc LSEFAIL                                                       */
      __IM  uint32_t HSEFAIL    : 1;            /*!< [6..6] desc HSEFAIL                                                       */
      __IM  uint32_t LSEFAULT   : 1;            /*!< [7..7] desc LSEFAULT                                                      */
      __IM  uint32_t HSEFAULT   : 1;            /*!< [8..8] desc HSEFAULT                                                      */
      __IM  uint32_t            : 2;
      __IM  uint32_t HSISTABLE  : 1;            /*!< [11..11] desc HSISTABLE                                                   */
      __IM  uint32_t HSESTABLE  : 1;            /*!< [12..12] desc HSESTABLE                                                   */
      __IM  uint32_t PLLSTABLE  : 1;            /*!< [13..13] desc PLLSTABLE                                                   */
      __IM  uint32_t LSISTABLE  : 1;            /*!< [14..14] desc LSISTABLE                                                   */
      __IM  uint32_t LSESTABLE  : 1;            /*!< [15..15] desc LSESTABLE                                                   */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000014) Interupt Clear Reg                                         */
    
    struct {
      __IOM uint32_t HSIRDY     : 1;            /*!< [0..0] desc HSIRDY                                                        */
      __IOM uint32_t HSERDY     : 1;            /*!< [1..1] desc HSERDY                                                        */
      __IOM uint32_t PLLRDY     : 1;            /*!< [2..2] desc PLLRDY                                                        */
      __IOM uint32_t LSIRDY     : 1;            /*!< [3..3] desc LSIRDY                                                        */
      __IOM uint32_t LSERDY     : 1;            /*!< [4..4] desc LSERDY                                                        */
      __IOM uint32_t LSEFAIL    : 1;            /*!< [5..5] desc LSEFAIL                                                       */
      __IOM uint32_t HSEFAIL    : 1;            /*!< [6..6] desc HSEFAIL                                                       */
      __IOM uint32_t LSEFAULT   : 1;            /*!< [7..7] desc LSEFAULT                                                      */
      __IOM uint32_t HSEFAULT   : 1;            /*!< [8..8] desc HSEFAULT                                                      */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t HSI;                         /*!< (@ 0x00000018) HSI Control Reg                                            */
    
    struct {
      __IOM uint32_t TRIM       : 11;           /*!< [10..0] desc TRIM                                                         */
      __IOM uint32_t DIV        : 4;            /*!< [14..11] desc DIV                                                         */
      __IM  uint32_t STABLE     : 1;            /*!< [15..15] desc STABLE                                                      */
    } HSI_f;
  } ;
  
  union {
    __IOM uint32_t HSE;                         /*!< (@ 0x0000001C) HSE Control Reg                                            */
    
    struct {
      __IOM uint32_t DRIVER     : 2;            /*!< [1..0] desc DRIVER                                                        */
      __IOM uint32_t FREQ       : 2;            /*!< [3..2] desc FREQ                                                          */
      __IOM uint32_t WAITCYCLE  : 2;            /*!< [5..4] desc WAITCYCLE                                                     */
      __IOM uint32_t MODE       : 1;            /*!< [6..6] desc MODE                                                          */
      __IOM uint32_t FLT        : 1;            /*!< [7..7] desc FLT                                                           */
      __IOM uint32_t DETCNT     : 11;           /*!< [18..8] desc DETCNT                                                       */
      __IM  uint32_t STABLE     : 1;            /*!< [19..19] desc STABLE                                                      */
    } HSE_f;
  } ;
  
  union {
    __IOM uint32_t LSI;                         /*!< (@ 0x00000020) LSI Control Reg                                            */
    
    struct {
      __IOM uint32_t TRIM       : 10;           /*!< [9..0] desc TRIM                                                          */
      __IOM uint32_t WAITCYCLE  : 2;            /*!< [11..10] desc WAITCYCLE                                                   */
      __IM  uint32_t            : 3;
      __IM  uint32_t STABLE     : 1;            /*!< [15..15] desc STABLE                                                      */
    } LSI_f;
  } ;
  
  union {
    __IOM uint32_t LSE;                         /*!< (@ 0x00000024) LSE Control Reg                                            */
    
    struct {
      __IOM uint32_t DRIVER     : 2;            /*!< [1..0] desc DRIVER                                                        */
      __IOM uint32_t AMP        : 2;            /*!< [3..2] desc AMP                                                           */
      __IOM uint32_t WAITCYCLE  : 2;            /*!< [5..4] desc WAITCYCLE                                                     */
      __IOM uint32_t MODE       : 1;            /*!< [6..6] desc MODE                                                          */
      __IM  uint32_t            : 8;
      __IM  uint32_t STABLE     : 1;            /*!< [15..15] desc STABLE                                                      */
    } LSE_f;
  } ;
  
  union {
    __IOM uint32_t PLL;                         /*!< (@ 0x00000028) PLL Control Reg                                            */
    
    struct {
      __IOM uint32_t SOURCE     : 2;            /*!< [1..0] desc SOURCE                                                        */
      __IOM uint32_t FREQIN     : 2;            /*!< [3..2] desc FREQIN                                                        */
      __IOM uint32_t MUL        : 5;            /*!< [8..4] desc MUL                                                           */
      __IOM uint32_t FREQOUT    : 3;            /*!< [11..9] desc FREQOUT                                                      */
      __IOM uint32_t WAITCYCLE  : 3;            /*!< [14..12] desc WAITCYCLE                                                   */
      __IM  uint32_t STABLE     : 1;            /*!< [15..15] desc STABLE                                                      */
      __IOM uint32_t RFU        : 4;            /*!< [19..16] desc RFU                                                         */
    } PLL_f;
  } ;
  
  union {
    __IOM uint32_t DEBUG;                       /*!< (@ 0x0000002C) Debug Control Reg                                          */
    
    struct {
      __IOM uint32_t ATIM       : 1;            /*!< [0..0] desc ATIM                                                          */
      __IOM uint32_t GTIM1      : 1;            /*!< [1..1] desc GTIM1                                                         */
      __IOM uint32_t GTIM2      : 1;            /*!< [2..2] desc GTIM2                                                         */
      __IOM uint32_t GTIM3      : 1;            /*!< [3..3] desc GTIM3                                                         */
      __IOM uint32_t GTIM4      : 1;            /*!< [4..4] desc GTIM4                                                         */
      __IOM uint32_t BTIM123    : 1;            /*!< [5..5] desc BTIM123                                                       */
      __IOM uint32_t AWT        : 1;            /*!< [6..6] desc AWT                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t RTC        : 1;            /*!< [8..8] desc RTC                                                           */
      __IOM uint32_t IWDT       : 1;            /*!< [9..9] desc IWDT                                                          */
      __IOM uint32_t WWDT       : 1;            /*!< [10..10] desc WWDT                                                        */
    } DEBUG_f;
  } ;
  
  union {
    __IOM uint32_t AHBEN;                       /*!< (@ 0x00000030) AHB Clock Control Reg                                      */
    
    struct {
      __IOM uint32_t DMA        : 1;            /*!< [0..0] desc DMA                                                           */
      __IOM uint32_t FLASH      : 1;            /*!< [1..1] desc FLASH                                                         */
      __IOM uint32_t CRC        : 1;            /*!< [2..2] desc CRC                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t GPIOA      : 1;            /*!< [4..4] desc GPIOA                                                         */
      __IOM uint32_t GPIOB      : 1;            /*!< [5..5] desc GPIOB                                                         */
      __IOM uint32_t GPIOC      : 1;            /*!< [6..6] desc GPIOC                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t GPIOF      : 1;            /*!< [9..9] desc GPIOF                                                         */
    } AHBEN_f;
  } ;
  
  union {
    __IOM uint32_t APBEN2;                      /*!< (@ 0x00000034) APB Clock Control Reg2                                     */
    
    struct {
      __IM  uint32_t            : 2;
      __IOM uint32_t ADC        : 1;            /*!< [2..2] desc ADC                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t VC         : 1;            /*!< [4..4] desc VC                                                            */
      __IM  uint32_t            : 2;
      __IOM uint32_t ATIM       : 1;            /*!< [7..7] desc ATIM                                                          */
      __IOM uint32_t SPI1       : 1;            /*!< [8..8] desc SPI1                                                          */
      __IOM uint32_t UART1      : 1;            /*!< [9..9] desc UART1                                                         */
      __IOM uint32_t GTIM3      : 1;            /*!< [10..10] desc GTIM3                                                       */
      __IOM uint32_t GTIM4      : 1;            /*!< [11..11] desc GTIM4                                                       */
      __IOM uint32_t BTIM       : 1;            /*!< [12..12] desc BTIM                                                        */
      __IOM uint32_t AWT        : 1;            /*!< [13..13] desc AWT                                                         */
    } APBEN2_f;
  } ;
  
  union {
    __IOM uint32_t APBEN1;                      /*!< (@ 0x00000038) APB Clock Control Reg1                                     */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t GTIM1      : 1;            /*!< [1..1] desc GTIM1                                                         */
      __IOM uint32_t GTIM2      : 1;            /*!< [2..2] desc GTIM2                                                         */
      __IOM uint32_t RTC        : 1;            /*!< [3..3] desc RTC                                                           */
      __IOM uint32_t WWDT       : 1;            /*!< [4..4] desc WWDT                                                          */
      __IOM uint32_t IWDT       : 1;            /*!< [5..5] desc IWDT                                                          */
      __IOM uint32_t SPI2       : 1;            /*!< [6..6] desc SPI2                                                          */
      __IOM uint32_t UART2      : 1;            /*!< [7..7] desc UART2                                                         */
      __IOM uint32_t UART3      : 1;            /*!< [8..8] desc UART3                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t I2C1       : 1;            /*!< [11..11] desc I2C1                                                        */
      __IOM uint32_t I2C2       : 1;            /*!< [12..12] desc I2C2                                                        */
    } APBEN1_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t AHBRST;                      /*!< (@ 0x00000040) AHB Reset Control Reg                                      */
    
    struct {
      __IOM uint32_t DMA        : 1;            /*!< [0..0] desc DMA                                                           */
      __IOM uint32_t FLASH      : 1;            /*!< [1..1] desc FLASH                                                         */
      __IOM uint32_t CRC        : 1;            /*!< [2..2] desc CRC                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t GPIOA      : 1;            /*!< [4..4] desc GPIOA                                                         */
      __IOM uint32_t GPIOB      : 1;            /*!< [5..5] desc GPIOB                                                         */
      __IOM uint32_t GPIOC      : 1;            /*!< [6..6] desc GPIOC                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t GPIOF      : 1;            /*!< [9..9] desc GPIOF                                                         */
    } AHBRST_f;
  } ;
  
  union {
    __IOM uint32_t APBRST2;                     /*!< (@ 0x00000044) APB Reset Control Reg2                                     */
    
    struct {
      __IM  uint32_t            : 2;
      __IOM uint32_t ADC        : 1;            /*!< [2..2] desc ADC                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t VC         : 1;            /*!< [4..4] desc VC                                                            */
      __IM  uint32_t            : 2;
      __IOM uint32_t ATIM       : 1;            /*!< [7..7] desc ATIM                                                          */
      __IOM uint32_t SPI1       : 1;            /*!< [8..8] desc SPI1                                                          */
      __IOM uint32_t UART1      : 1;            /*!< [9..9] desc UART1                                                         */
      __IOM uint32_t GTIM3      : 1;            /*!< [10..10] desc GTIM3                                                       */
      __IOM uint32_t GTIM4      : 1;            /*!< [11..11] desc GTIM4                                                       */
      __IOM uint32_t BTIM       : 1;            /*!< [12..12] desc BTIM                                                        */
      __IOM uint32_t AWT        : 1;            /*!< [13..13] desc AWT                                                         */
    } APBRST2_f;
  } ;
  
  union {
    __IOM uint32_t APBRST1;                     /*!< (@ 0x00000048) APB Reset Control Reg1                                     */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t GTIM1      : 1;            /*!< [1..1] desc GTIM1                                                         */
      __IOM uint32_t GTIM2      : 1;            /*!< [2..2] desc GTIM2                                                         */
      __IOM uint32_t RTC        : 1;            /*!< [3..3] desc RTC                                                           */
      __IOM uint32_t WWDT       : 1;            /*!< [4..4] desc WWDT                                                          */
      __IOM uint32_t IWDT       : 1;            /*!< [5..5] desc IWDT                                                          */
      __IOM uint32_t SPI2       : 1;            /*!< [6..6] desc SPI2                                                          */
      __IOM uint32_t UART2      : 1;            /*!< [7..7] desc UART2                                                         */
      __IOM uint32_t UART3      : 1;            /*!< [8..8] desc UART3                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t I2C1       : 1;            /*!< [11..11] desc I2C1                                                        */
      __IOM uint32_t I2C2       : 1;            /*!< [12..12] desc I2C2                                                        */
    } APBRST1_f;
  } ;
  
  union {
    __IOM uint32_t RESETFLAG;                   /*!< (@ 0x0000004C) Reset Status Reg                                           */
    
    struct {
      __IOM uint32_t POR        : 1;            /*!< [0..0] desc POR                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t LVD        : 1;            /*!< [3..3] desc LVD                                                           */
      __IOM uint32_t IWDT       : 1;            /*!< [4..4] desc IWDT                                                          */
      __IOM uint32_t WWDT       : 1;            /*!< [5..5] desc WWDT                                                          */
      __IOM uint32_t RSTB       : 1;            /*!< [6..6] desc RSTB                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t LOCKUP     : 1;            /*!< [8..8] desc LOCKUP                                                        */
      __IOM uint32_t SYSRESETREQ : 1;           /*!< [9..9] desc SYSRESETREQ                                                   */
    } RESETFLAG_f;
  } ;
  
  union {
    __IOM uint32_t GTIM1CAP;                    /*!< (@ 0x00000050) GTIM1 CAP Control Reg                                      */
    
    struct {
      __IOM uint32_t CH1        : 3;            /*!< [2..0] desc CH1                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH2        : 3;            /*!< [6..4] desc CH2                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH3        : 3;            /*!< [10..8] desc CH3                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH4        : 3;            /*!< [14..12] desc CH4                                                         */
    } GTIM1CAP_f;
  } ;
  
  union {
    __IOM uint32_t GTIM2CAP;                    /*!< (@ 0x00000054) GTIM2 CAP Control Reg                                      */
    
    struct {
      __IOM uint32_t CH1        : 3;            /*!< [2..0] desc CH1                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH2        : 3;            /*!< [6..4] desc CH2                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH3        : 3;            /*!< [10..8] desc CH3                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH4        : 3;            /*!< [14..12] desc CH4                                                         */
    } GTIM2CAP_f;
  } ;
  
  union {
    __IOM uint32_t GTIM3CAP;                    /*!< (@ 0x00000058) GTIM3 CAP Control Reg                                      */
    
    struct {
      __IOM uint32_t CH1        : 3;            /*!< [2..0] desc CH1                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH2        : 3;            /*!< [6..4] desc CH2                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH3        : 3;            /*!< [10..8] desc CH3                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH4        : 3;            /*!< [14..12] desc CH4                                                         */
    } GTIM3CAP_f;
  } ;
  
  union {
    __IOM uint32_t GTIM4CAP;                    /*!< (@ 0x0000005C) GTIM4 CAP Control Reg                                      */
    
    struct {
      __IOM uint32_t CH1        : 3;            /*!< [2..0] desc CH1                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH2        : 3;            /*!< [6..4] desc CH2                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH3        : 3;            /*!< [10..8] desc CH3                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH4        : 3;            /*!< [14..12] desc CH4                                                         */
    } GTIM4CAP_f;
  } ;
  
  union {
    __IOM uint32_t ATIMETR;                     /*!< (@ 0x00000060) ATIM ETR Control Reg                                       */
    
    struct {
      __IOM uint32_t ATIMETR    : 3;            /*!< [2..0] desc ATIMETR                                                       */
    } ATIMETR_f;
  } ;
  
  union {
    __IOM uint32_t GTIMETR;                     /*!< (@ 0x00000064) GTIM1-4 ETR Control Reg                                    */
    
    struct {
      __IOM uint32_t GTIM1ETR   : 3;            /*!< [2..0] desc GTIM1ETR                                                      */
      __IM  uint32_t            : 1;
      __IOM uint32_t GTIM2ETR   : 3;            /*!< [6..4] desc GTIM2ETR                                                      */
      __IM  uint32_t            : 1;
      __IOM uint32_t GTIM3ETR   : 3;            /*!< [10..8] desc GTIM3ETR                                                     */
      __IM  uint32_t            : 1;
      __IOM uint32_t GTIM4ETR   : 3;            /*!< [14..12] desc GTIM4ETR                                                    */
    } GTIMETR_f;
  } ;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t TIMITR;                      /*!< (@ 0x0000006C) BTIMx GTIMx ATIM ITR Control Reg                           */
    
    struct {
      __IOM uint32_t ATIMITR    : 3;            /*!< [2..0] desc ATIMITR                                                       */
      __IOM uint32_t GTIM1ITR   : 3;            /*!< [5..3] desc GTIM1ITR                                                      */
      __IOM uint32_t GTIM2ITR   : 3;            /*!< [8..6] desc GTIM2ITR                                                      */
      __IOM uint32_t GTIM3ITR   : 3;            /*!< [11..9] desc GTIM3ITR                                                     */
      __IOM uint32_t GTIM4ITR   : 3;            /*!< [14..12] desc GTIM4ITR                                                    */
      __IOM uint32_t BTIM1ITR   : 3;            /*!< [17..15] desc BTIM1ITR                                                    */
      __IOM uint32_t BTIM2ITR   : 3;            /*!< [20..18] desc BTIM2ITR                                                    */
      __IOM uint32_t BTIM3ITR   : 3;            /*!< [23..21] desc BTIM3ITR                                                    */
    } TIMITR_f;
  } ;
  
  union {
    __IOM uint32_t MCO;                         /*!< (@ 0x00000070) Master Clock Output Control Reg                            */
    
    struct {
      __IOM uint32_t SOURCE     : 4;            /*!< [3..0] desc SOURCE                                                        */
      __IOM uint32_t DIV        : 3;            /*!< [6..4] desc DIV                                                           */
    } MCO_f;
  } ;
  
  union {
    __IOM uint32_t IRMOD;                       /*!< (@ 0x00000074) IR MOD Control Reg                                         */
    
    struct {
      __IOM uint32_t MOD        : 4;            /*!< [3..0] desc MOD                                                           */
    } IRMOD_f;
  } ;
} SYSCTRL_TypeDef;                                 /*!< Size = 120 (0x78)                                                         */



/* =========================================================================================================================== */
/* ================                                           UART1                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc UART1 (UART1)
  */

typedef struct {                                /*!< (@ 0x40013800) UART1 Structure                                            */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t TXEN       : 1;            /*!< [0..0] desc TXEN                                                          */
      __IOM uint32_t RXEN       : 1;            /*!< [1..1] desc RXEN                                                          */
      __IOM uint32_t PARITY     : 2;            /*!< [3..2] desc PARITY                                                        */
      __IOM uint32_t STOP       : 2;            /*!< [5..4] desc STOP                                                          */
      __IOM uint32_t SYNC       : 1;            /*!< [6..6] desc SYNC                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t START      : 1;            /*!< [8..8] desc START                                                         */
      __IOM uint32_t OVER       : 2;            /*!< [10..9] desc OVER                                                         */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) Control register2                                          */
    
    struct {
      __IOM uint32_t ADDREN     : 1;            /*!< [0..0] desc ADDREN                                                        */
      __IOM uint32_t SIGNAL     : 1;            /*!< [1..1] desc SIGNAL                                                        */
      __IOM uint32_t CTSEN      : 1;            /*!< [2..2] desc CTSEN                                                         */
      __IOM uint32_t RTSEN      : 1;            /*!< [3..3] desc RTSEN                                                         */
      __IOM uint32_t RXINV      : 1;            /*!< [4..4] desc RXINV                                                         */
      __IOM uint32_t TXINV      : 1;            /*!< [5..5] desc TXINV                                                         */
      __IOM uint32_t DMARX      : 1;            /*!< [6..6] desc DMARX                                                         */
      __IOM uint32_t DMATX      : 1;            /*!< [7..7] desc DMATX                                                         */
      __IOM uint32_t SOURCE     : 2;            /*!< [9..8] desc SOURCE                                                        */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000008) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t TXE        : 1;            /*!< [0..0] TxBuf empty                                                        */
      __IOM uint32_t TC         : 1;            /*!< [1..1] Transmit complete                                                  */
      __IOM uint32_t RC         : 1;            /*!< [2..2] Receive complete                                                   */
      __IOM uint32_t FE         : 1;            /*!< [3..3] Frame error                                                        */
      __IOM uint32_t PE         : 1;            /*!< [4..4] Parity error                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t CTS        : 1;            /*!< [6..6] CTS change                                                         */
    } IER_f;
  } ;
  
  union {
    __IOM uint32_t BRRI;                        /*!< (@ 0x0000000C) desc BRRI                                                  */
    
    struct {
      __IOM uint32_t BRRI       : 16;           /*!< [15..0] desc BRRI                                                         */
    } BRRI_f;
  } ;
  
  union {
    __IOM uint32_t BRRF;                        /*!< (@ 0x00000010) desc BRRF                                                  */
    
    struct {
      __IOM uint32_t BRRF       : 4;            /*!< [3..0] desc BRRF                                                          */
    } BRRF_f;
  } ;
  __IM  uint32_t  RESERVED[2];
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x0000001C) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t TXE        : 1;            /*!< [0..0] TxBuf empty                                                        */
      __IM  uint32_t TC         : 1;            /*!< [1..1] Transmit complete                                                  */
      __IM  uint32_t RC         : 1;            /*!< [2..2] Receive complete                                                   */
      __IM  uint32_t FE         : 1;            /*!< [3..3] Frame error                                                        */
      __IM  uint32_t PE         : 1;            /*!< [4..4] Parity error                                                       */
      __IM  uint32_t MATCH      : 1;            /*!< [5..5] Slave addr match                                                   */
      __IM  uint32_t CTS        : 1;            /*!< [6..6] CTS change                                                         */
      __IM  uint32_t CTSLV      : 1;            /*!< [7..7] CTS PIN level                                                      */
      __IM  uint32_t TXBUSY     : 1;            /*!< [8..8] desc TXBUSY                                                        */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000020) Interrupt flag clear register                              */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t TC         : 1;            /*!< [1..1] Transmit complete                                                  */
      __IOM uint32_t RC         : 1;            /*!< [2..2] Receive complete                                                   */
      __IOM uint32_t FE         : 1;            /*!< [3..3] Frame error                                                        */
      __IOM uint32_t PE         : 1;            /*!< [4..4] Parity error                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t CTS        : 1;            /*!< [6..6] CTS change                                                         */
    } ICR_f;
  } ;
  
  union {
    __IM  uint32_t RDR;                         /*!< (@ 0x00000024) Data reg for read                                          */
    
    struct {
      __IM  uint32_t RDR        : 9;            /*!< [8..0] desc RDR                                                           */
    } RDR_f;
  } ;
  
  union {
    __OM  uint32_t TDR;                         /*!< (@ 0x00000028) Data reg for write                                         */
    
    struct {
      __OM  uint32_t TDR        : 9;            /*!< [8..0] desc TDR                                                           */
    } TDR_f;
  } ;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t ADDR;                        /*!< (@ 0x00000030) Slave addr                                                 */
    
    struct {
      __IOM uint32_t ADDR       : 8;            /*!< [7..0] desc ADDR                                                          */
    } ADDR_f;
  } ;
  
  union {
    __IOM uint32_t MASK;                        /*!< (@ 0x00000034) Slave addr mask                                            */
    
    struct {
      __IOM uint32_t MASK       : 8;            /*!< [7..0] desc MASK                                                          */
    } MASK_f;
  } ;




} UART_TypeDef;                                    /*!< Size = 56 (0x38)                                                          */



/* =========================================================================================================================== */
/* ================                                            VC1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc VC1 (VC1)
  */

typedef struct {                                /*!< (@ 0x40012A00) VC1 Structure                                              */
  
  union {
    __IOM uint32_t DIV;                         /*!< (@ 0x00000000) desc DIV                                                   */
    
    struct {
      __IOM uint32_t DIV        : 6;            /*!< [5..0] desc DIV                                                           */
      __IOM uint32_t EN         : 1;            /*!< [6..6] desc EN                                                            */
      __IOM uint32_t VIN        : 1;            /*!< [7..7] desc VIN                                                           */
    } DIV_f;
  } ;
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000004) Control register0                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t RESP       : 2;            /*!< [2..1] desc RESP                                                          */
      __IOM uint32_t HYS        : 2;            /*!< [4..3] desc HYS                                                           */
      __IOM uint32_t IE         : 1;            /*!< [5..5] desc IE                                                            */
      __IOM uint32_t POL        : 1;            /*!< [6..6] desc POL                                                           */
      __IOM uint32_t WINDOW     : 1;            /*!< [7..7] desc WINDOW                                                        */
      __IOM uint32_t INP        : 4;            /*!< [11..8] desc INP                                                          */
      __IOM uint32_t INN        : 4;            /*!< [15..12] desc INN                                                         */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000008) Control register1                                          */
    
    struct {
      __IOM uint32_t FLTEN      : 1;            /*!< [0..0] desc FLTEN                                                         */
      __IOM uint32_t FLTTIME    : 3;            /*!< [3..1] desc FLTTIME                                                       */
      __IOM uint32_t FLTCLK     : 1;            /*!< [4..4] desc FLTCLK                                                        */
      __IOM uint32_t FALLIE     : 1;            /*!< [5..5] desc FALLIE                                                        */
      __IOM uint32_t RISEIE     : 1;            /*!< [6..6] desc RISEIE                                                        */
      __IOM uint32_t HIGHIE     : 1;            /*!< [7..7] desc HIGHIE                                                        */
      __IOM uint32_t ATIMCLR    : 1;            /*!< [8..8] desc ATIMCLR                                                       */
      __IOM uint32_t ATIMBK     : 1;            /*!< [9..9] desc ATIMBK                                                        */
      __IOM uint32_t BLANKCH1B  : 1;            /*!< [10..10] desc BLANKCH1B                                                   */
      __IOM uint32_t BLANKCH2B  : 1;            /*!< [11..11] desc BLANKCH2B                                                   */
      __IOM uint32_t BLANKCH3B  : 1;            /*!< [12..12] desc BLANKCH3B                                                   */
      __IOM uint32_t BLANKFLT   : 3;            /*!< [15..13] desc BLANKFLT                                                    */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x0000000C) Status register                                            */
    
    struct {
      __IOM uint32_t INTF       : 1;            /*!< [0..0] desc INTF                                                          */
      __IM  uint32_t FLTV       : 1;            /*!< [1..1] desc FLTV                                                          */
      __IM  uint32_t READY      : 1;            /*!< [2..2] desc READY                                                         */
    } SR_f;
  } ;
} VC_TypeDef;                                      /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           WWDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc WWDT (WWDT)
  */

typedef struct {                                /*!< (@ 0x40002C00) WWDT Structure                                             */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t WCNT       : 7;            /*!< [6..0] desc WCNT                                                          */
      __IOM uint32_t EN         : 1;            /*!< [7..7] desc EN                                                            */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) Control register2                                          */
    
    struct {
      __IOM uint32_t WINR       : 7;            /*!< [6..0] desc WINR                                                          */
      __IOM uint32_t PRS        : 3;            /*!< [9..7] desc PRS                                                           */
      __IOM uint32_t IE         : 1;            /*!< [10..10] desc IE                                                          */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x00000008) Status register                                            */
    
    struct {
      __IOM uint32_t POV        : 1;            /*!< [0..0] desc POV                                                           */
    } SR_f;
  } ;
} WWDT_TypeDef;                                    /*!< Size = 12 (0xc)                                                           */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define ADC_BASE                    0x40012400UL
#define ATIM_BASE                   0x40012C00UL
#define AWT_BASE                    0x40014C00UL
#define BTIM1_BASE                  0x40014800UL
#define BTIM2_BASE                  0x40014900UL
#define BTIM3_BASE                  0x40014A00UL
#define CRC_BASE                    0x40023000UL
#define DMA_BASE                    0x40020000UL
#define DMACHANNEL1_BASE            0x40020020UL
#define DMACHANNEL2_BASE            0x40020040UL
#define DMACHANNEL3_BASE            0x40020060UL
#define DMACHANNEL4_BASE            0x40020080UL
#define DMACHANNEL5_BASE            0x400200A0UL
#define FLASH_BASE                  0x40022000UL
#define GPIOA_BASE                  0x48000000UL
#define GPIOB_BASE                  0x48000400UL
#define GPIOC_BASE                  0x48000800UL
#define GPIOF_BASE                  0x48001400UL
#define GTIM1_BASE                  0x40000400UL
#define GTIM2_BASE                  0x40001000UL
#define GTIM3_BASE                  0x40014000UL
#define GTIM4_BASE                  0x40014400UL
#define I2C1_BASE                   0x40005400UL
#define I2C2_BASE                   0x40005800UL
#define IWDT_BASE                   0x40003000UL
#define LVD_BASE                    0x40012A80UL
#define RAM_BASE                    0x40022400UL
#define RTC_BASE                    0x40002800UL
#define SPI1_BASE                   0x40013000UL
#define SPI2_BASE                   0x40003800UL
#define SYSCTRL_BASE                0x40010000UL
#define UART1_BASE                  0x40013800UL
#define UART2_BASE                  0x40004400UL
#define UART3_BASE                  0x40004800UL
#define VC1_BASE                    0x40012A00UL
#define VC2_BASE                    0x40012A10UL
#define WWDT_BASE                   0x40002C00UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define M0P_ADC                         ((ADC_TypeDef*)               ADC_BASE)
#define M0P_ATIM                        ((ATIM_TypeDef*)              ATIM_BASE)
#define M0P_AWT                         ((AWT_TypeDef*)               AWT_BASE)
#define M0P_BTIM1                       ((BTIM_TypeDef*)              BTIM1_BASE)
#define M0P_BTIM2                       ((BTIM_TypeDef*)              BTIM2_BASE)
#define M0P_BTIM3                       ((BTIM_TypeDef*)              BTIM3_BASE)
#define M0P_CRC                         ((CRC_TypeDef*)               CRC_BASE)
#define M0P_DMA                         ((DMA_TypeDef*)               DMA_BASE)
#define M0P_DMACHANNEL1                 ((DMACHANNEL_TypeDef*)        DMACHANNEL1_BASE)
#define M0P_DMACHANNEL2                 ((DMACHANNEL_TypeDef*)        DMACHANNEL2_BASE)
#define M0P_DMACHANNEL3                 ((DMACHANNEL_TypeDef*)        DMACHANNEL3_BASE)
#define M0P_DMACHANNEL4                 ((DMACHANNEL_TypeDef*)        DMACHANNEL4_BASE)
#define M0P_DMACHANNEL5                 ((DMACHANNEL_TypeDef*)        DMACHANNEL5_BASE)
#define M0P_FLASH                       ((FLASH_TypeDef*)             FLASH_BASE)
#define M0P_GPIOA                       ((GPIO_TypeDef*)              GPIOA_BASE)
#define M0P_GPIOB                       ((GPIO_TypeDef*)              GPIOB_BASE)
#define M0P_GPIOC                       ((GPIO_TypeDef*)             GPIOC_BASE)
#define M0P_GPIOF                       ((GPIO_TypeDef*)             GPIOF_BASE)
#define M0P_GTIM1                       ((GTIM_TypeDef*)              GTIM1_BASE)
#define M0P_GTIM2                       ((GTIM_TypeDef*)              GTIM2_BASE)
#define M0P_GTIM3                       ((GTIM_TypeDef*)              GTIM3_BASE)
#define M0P_GTIM4                       ((GTIM_TypeDef*)              GTIM4_BASE)
#define M0P_I2C1                        ((I2C_TypeDef*)               I2C1_BASE)
#define M0P_I2C2                        ((I2C_TypeDef*)               I2C2_BASE)
#define M0P_IWDT                        ((IWDT_TypeDef*)              IWDT_BASE)
#define M0P_LVD                         ((LVD_TypeDef*)               LVD_BASE)
#define M0P_RAM                         ((RAM_TypeDef*)               RAM_BASE)
#define M0P_RTC                         ((RTC_TypeDef*)               RTC_BASE)
#define M0P_SPI1                        ((SPI_TypeDef*)               SPI1_BASE)
#define M0P_SPI2                        ((SPI_TypeDef*)               SPI2_BASE)
#define M0P_SYSCTRL                     ((SYSCTRL_TypeDef*)           SYSCTRL_BASE)
#define M0P_UART1                       ((UART_TypeDef*)              UART1_BASE)
#define M0P_UART2                       ((UART_TypeDef*)              UART2_BASE)
#define M0P_UART3                       ((UART_TypeDef*)              UART3_BASE)
#define M0P_VC1                         ((VC_TypeDef*)                VC1_BASE)
#define M0P_VC2                         ((VC_TypeDef*)                VC2_BASE)
#define M0P_WWDT                        ((WWDT_TypeDef*)              WWDT_BASE)

#define CW_ADC                          M0P_ADC        
#define CW_ATIM                         M0P_ATIM       
#define CW_AWT                          M0P_AWT        
#define CW_BTIM1                        M0P_BTIM1      
#define CW_BTIM2                        M0P_BTIM2      
#define CW_BTIM3                        M0P_BTIM3      
#define CW_CRC                          M0P_CRC        
#define CW_DMA                          M0P_DMA        
#define CW_DMACHANNEL1                  M0P_DMACHANNEL1
#define CW_DMACHANNEL2                  M0P_DMACHANNEL2
#define CW_DMACHANNEL3                  M0P_DMACHANNEL3
#define CW_DMACHANNEL4                  M0P_DMACHANNEL4
#define CW_DMACHANNEL5                  M0P_DMACHANNEL5
#define CW_FLASH                        M0P_FLASH      
#define CW_GPIOA                        M0P_GPIOA      
#define CW_GPIOB                        M0P_GPIOB      
#define CW_GPIOC                        M0P_GPIOC      
#define CW_GPIOF                        M0P_GPIOF      
#define CW_GTIM1                        M0P_GTIM1      
#define CW_GTIM2                        M0P_GTIM2      
#define CW_GTIM3                        M0P_GTIM3      
#define CW_GTIM4                        M0P_GTIM4      
#define CW_I2C1                         M0P_I2C1       
#define CW_I2C2                         M0P_I2C2       
#define CW_IWDT                         M0P_IWDT       
#define CW_LVD                          M0P_LVD        
#define CW_RAM                          M0P_RAM        
#define CW_RTC                          M0P_RTC        
#define CW_SPI1                         M0P_SPI1       
#define CW_SPI2                         M0P_SPI2       
#define CW_SYSCTRL                      M0P_SYSCTRL    
#define CW_UART1                        M0P_UART1      
#define CW_UART2                        M0P_UART2      
#define CW_UART3                        M0P_UART3      
#define CW_VC1                          M0P_VC1        
#define CW_VC2                          M0P_VC2        
#define CW_WWDT                         M0P_WWDT       

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define ADC_CR0_BIAS_Pos                  (14UL)                    /*!< BIAS (Bit 14)                                         */
#define ADC_CR0_BIAS_Msk                  (0xc000UL)                /*!< BIAS (Bitfield-Mask: 0x03)                            */
#define ADC_CR0_BUF_Pos                   (13UL)                    /*!< BUF (Bit 13)                                          */
#define ADC_CR0_BUF_Msk                   (0x2000UL)                /*!< BUF (Bitfield-Mask: 0x01)                             */
#define ADC_CR0_SAM_Pos                   (11UL)                    /*!< SAM (Bit 11)                                          */
#define ADC_CR0_SAM_Msk                   (0x1800UL)                /*!< SAM (Bitfield-Mask: 0x03)                             */
#define ADC_CR0_CLK_Pos                   (8UL)                     /*!< CLK (Bit 8)                                           */
#define ADC_CR0_CLK_Msk                   (0x700UL)                 /*!< CLK (Bitfield-Mask: 0x07)                             */
#define ADC_CR0_REF_Pos                   (6UL)                     /*!< REF (Bit 6)                                           */
#define ADC_CR0_REF_Msk                   (0xc0UL)                  /*!< REF (Bitfield-Mask: 0x03)                             */
#define ADC_CR0_TSEN_Pos                  (5UL)                     /*!< TSEN (Bit 5)                                          */
#define ADC_CR0_TSEN_Msk                  (0x20UL)                  /*!< TSEN (Bitfield-Mask: 0x01)                            */
#define ADC_CR0_BGREN_Pos                 (4UL)                     /*!< BGREN (Bit 4)                                         */
#define ADC_CR0_BGREN_Msk                 (0x10UL)                  /*!< BGREN (Bitfield-Mask: 0x01)                           */
#define ADC_CR0_MODE_Pos                  (1UL)                     /*!< MODE (Bit 1)                                          */
#define ADC_CR0_MODE_Msk                  (0xeUL)                   /*!< MODE (Bitfield-Mask: 0x07)                            */
#define ADC_CR0_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define ADC_CR0_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR1  ========================================================== */
#define ADC_CR1_WDTALL_Pos                (13UL)                    /*!< WDTALL (Bit 13)                                       */
#define ADC_CR1_WDTALL_Msk                (0x2000UL)                /*!< WDTALL (Bitfield-Mask: 0x01)                          */
#define ADC_CR1_WDTCH_Pos                 (8UL)                     /*!< WDTCH (Bit 8)                                         */
#define ADC_CR1_WDTCH_Msk                 (0xf00UL)                 /*!< WDTCH (Bitfield-Mask: 0x0f)                           */
#define ADC_CR1_DMAEN_Pos                 (7UL)                     /*!< DMAEN (Bit 7)                                         */
#define ADC_CR1_DMAEN_Msk                 (0x80UL)                  /*!< DMAEN (Bitfield-Mask: 0x01)                           */
#define ADC_CR1_ALIGN_Pos                 (6UL)                     /*!< ALIGN (Bit 6)                                         */
#define ADC_CR1_ALIGN_Msk                 (0x40UL)                  /*!< ALIGN (Bitfield-Mask: 0x01)                           */
#define ADC_CR1_DISCARD_Pos               (5UL)                     /*!< DISCARD (Bit 5)                                       */
#define ADC_CR1_DISCARD_Msk               (0x20UL)                  /*!< DISCARD (Bitfield-Mask: 0x01)                         */
#define ADC_CR1_CHMUX_Pos                 (0UL)                     /*!< CHMUX (Bit 0)                                         */
#define ADC_CR1_CHMUX_Msk                 (0xfUL)                   /*!< CHMUX (Bitfield-Mask: 0x0f)                           */
/* =========================================================  START  ========================================================= */
#define ADC_START_AUTOSTOP_Pos            (1UL)                     /*!< AUTOSTOP (Bit 1)                                      */
#define ADC_START_AUTOSTOP_Msk            (0x2UL)                   /*!< AUTOSTOP (Bitfield-Mask: 0x01)                        */
#define ADC_START_START_Pos               (0UL)                     /*!< START (Bit 0)                                         */
#define ADC_START_START_Msk               (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SQR  ========================================================== */
#define ADC_SQR_ENS_Pos                   (16UL)                    /*!< ENS (Bit 16)                                          */
#define ADC_SQR_ENS_Msk                   (0x30000UL)               /*!< ENS (Bitfield-Mask: 0x03)                             */
#define ADC_SQR_SQR3_Pos                  (12UL)                    /*!< SQR3 (Bit 12)                                         */
#define ADC_SQR_SQR3_Msk                  (0xf000UL)                /*!< SQR3 (Bitfield-Mask: 0x0f)                            */
#define ADC_SQR_SQR2_Pos                  (8UL)                     /*!< SQR2 (Bit 8)                                          */
#define ADC_SQR_SQR2_Msk                  (0xf00UL)                 /*!< SQR2 (Bitfield-Mask: 0x0f)                            */
#define ADC_SQR_SQR1_Pos                  (4UL)                     /*!< SQR1 (Bit 4)                                          */
#define ADC_SQR_SQR1_Msk                  (0xf0UL)                  /*!< SQR1 (Bitfield-Mask: 0x0f)                            */
#define ADC_SQR_SQR0_Pos                  (0UL)                     /*!< SQR0 (Bit 0)                                          */
#define ADC_SQR_SQR0_Msk                  (0xfUL)                   /*!< SQR0 (Bitfield-Mask: 0x0f)                            */
/* ==========================================================  CR2  ========================================================== */
#define ADC_CR2_ACCRST_Pos                (9UL)                     /*!< ACCRST (Bit 9)                                        */
#define ADC_CR2_ACCRST_Msk                (0x200UL)                 /*!< ACCRST (Bitfield-Mask: 0x01)                          */
#define ADC_CR2_ACCEN_Pos                 (8UL)                     /*!< ACCEN (Bit 8)                                         */
#define ADC_CR2_ACCEN_Msk                 (0x100UL)                 /*!< ACCEN (Bitfield-Mask: 0x01)                           */
#define ADC_CR2_CNT_Pos                   (0UL)                     /*!< CNT (Bit 0)                                           */
#define ADC_CR2_CNT_Msk                   (0xffUL)                  /*!< CNT (Bitfield-Mask: 0xff)                             */
/* ==========================================================  VTH  ========================================================== */
#define ADC_VTH_VTH_Pos                   (0UL)                     /*!< VTH (Bit 0)                                           */
#define ADC_VTH_VTH_Msk                   (0xfffUL)                 /*!< VTH (Bitfield-Mask: 0xfff)                            */
/* ==========================================================  VTL  ========================================================== */
#define ADC_VTL_VTL_Pos                   (0UL)                     /*!< VTL (Bit 0)                                           */
#define ADC_VTL_VTL_Msk                   (0xfffUL)                 /*!< VTL (Bitfield-Mask: 0xfff)                            */
/* ========================================================  TRIGGER  ======================================================== */
#define ADC_TRIGGER_DMA_Pos               (15UL)                    /*!< DMA (Bit 15)                                          */
#define ADC_TRIGGER_DMA_Msk               (0x8000UL)                /*!< DMA (Bitfield-Mask: 0x01)                             */
#define ADC_TRIGGER_I2C2_Pos              (14UL)                    /*!< I2C2 (Bit 14)                                         */
#define ADC_TRIGGER_I2C2_Msk              (0x4000UL)                /*!< I2C2 (Bitfield-Mask: 0x01)                            */
#define ADC_TRIGGER_I2C1_Pos              (13UL)                    /*!< I2C1 (Bit 13)                                         */
#define ADC_TRIGGER_I2C1_Msk              (0x2000UL)                /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define ADC_TRIGGER_SPI2_Pos              (12UL)                    /*!< SPI2 (Bit 12)                                         */
#define ADC_TRIGGER_SPI2_Msk              (0x1000UL)                /*!< SPI2 (Bitfield-Mask: 0x01)                            */
#define ADC_TRIGGER_SPI1_Pos              (11UL)                    /*!< SPI1 (Bit 11)                                         */
#define ADC_TRIGGER_SPI1_Msk              (0x800UL)                 /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define ADC_TRIGGER_UART3_Pos             (10UL)                    /*!< UART3 (Bit 10)                                        */
#define ADC_TRIGGER_UART3_Msk             (0x400UL)                 /*!< UART3 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_UART2_Pos             (9UL)                     /*!< UART2 (Bit 9)                                         */
#define ADC_TRIGGER_UART2_Msk             (0x200UL)                 /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_UART1_Pos             (8UL)                     /*!< UART1 (Bit 8)                                         */
#define ADC_TRIGGER_UART1_Msk             (0x100UL)                 /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_BTIM3_Pos             (7UL)                     /*!< BTIM3 (Bit 7)                                         */
#define ADC_TRIGGER_BTIM3_Msk             (0x80UL)                  /*!< BTIM3 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_BTIM2_Pos             (6UL)                     /*!< BTIM2 (Bit 6)                                         */
#define ADC_TRIGGER_BTIM2_Msk             (0x40UL)                  /*!< BTIM2 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_BTIM1_Pos             (5UL)                     /*!< BTIM1 (Bit 5)                                         */
#define ADC_TRIGGER_BTIM1_Msk             (0x20UL)                  /*!< BTIM1 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_GTIM4_Pos             (4UL)                     /*!< GTIM4 (Bit 4)                                         */
#define ADC_TRIGGER_GTIM4_Msk             (0x10UL)                  /*!< GTIM4 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_GTIM3_Pos             (3UL)                     /*!< GTIM3 (Bit 3)                                         */
#define ADC_TRIGGER_GTIM3_Msk             (0x8UL)                   /*!< GTIM3 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_GTIM2_Pos             (2UL)                     /*!< GTIM2 (Bit 2)                                         */
#define ADC_TRIGGER_GTIM2_Msk             (0x4UL)                   /*!< GTIM2 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_GTIM1_Pos             (1UL)                     /*!< GTIM1 (Bit 1)                                         */
#define ADC_TRIGGER_GTIM1_Msk             (0x2UL)                   /*!< GTIM1 (Bitfield-Mask: 0x01)                           */
#define ADC_TRIGGER_ATIM_Pos              (0UL)                     /*!< ATIM (Bit 0)                                          */
#define ADC_TRIGGER_ATIM_Msk              (0x1UL)                   /*!< ATIM (Bitfield-Mask: 0x01)                            */
/* ========================================================  RESULT0  ======================================================== */
#define ADC_RESULT0_RESULT_Pos            (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULT0_RESULT_Msk            (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT1  ======================================================== */
#define ADC_RESULT1_RESULT_Pos            (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULT1_RESULT_Msk            (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT2  ======================================================== */
#define ADC_RESULT2_RESULT_Pos            (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULT2_RESULT_Msk            (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT3  ======================================================== */
#define ADC_RESULT3_RESULT_Pos            (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULT3_RESULT_Msk            (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* =======================================================  RESULTACC  ======================================================= */
#define ADC_RESULTACC_RESULT_Pos          (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULTACC_RESULT_Msk          (0xffffffUL)              /*!< RESULT (Bitfield-Mask: 0xffffff)                      */
/* ==========================================================  IER  ========================================================== */
#define ADC_IER_OVW_Pos                   (6UL)                     /*!< OVW (Bit 6)                                           */
#define ADC_IER_OVW_Msk                   (0x40UL)                  /*!< OVW (Bitfield-Mask: 0x01)                             */
#define ADC_IER_WDTR_Pos                  (5UL)                     /*!< WDTR (Bit 5)                                          */
#define ADC_IER_WDTR_Msk                  (0x20UL)                  /*!< WDTR (Bitfield-Mask: 0x01)                            */
#define ADC_IER_WDTH_Pos                  (4UL)                     /*!< WDTH (Bit 4)                                          */
#define ADC_IER_WDTH_Msk                  (0x10UL)                  /*!< WDTH (Bitfield-Mask: 0x01)                            */
#define ADC_IER_WDTL_Pos                  (3UL)                     /*!< WDTL (Bit 3)                                          */
#define ADC_IER_WDTL_Msk                  (0x8UL)                   /*!< WDTL (Bitfield-Mask: 0x01)                            */
#define ADC_IER_EOA_Pos                   (2UL)                     /*!< EOA (Bit 2)                                           */
#define ADC_IER_EOA_Msk                   (0x4UL)                   /*!< EOA (Bitfield-Mask: 0x01)                             */
#define ADC_IER_EOS_Pos                   (1UL)                     /*!< EOS (Bit 1)                                           */
#define ADC_IER_EOS_Msk                   (0x2UL)                   /*!< EOS (Bitfield-Mask: 0x01)                             */
#define ADC_IER_EOC_Pos                   (0UL)                     /*!< EOC (Bit 0)                                           */
#define ADC_IER_EOC_Msk                   (0x1UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define ADC_ISR_READY_Pos                 (7UL)                     /*!< READY (Bit 7)                                         */
#define ADC_ISR_READY_Msk                 (0x80UL)                  /*!< READY (Bitfield-Mask: 0x01)                           */
#define ADC_ISR_OVW_Pos                   (6UL)                     /*!< OVW (Bit 6)                                           */
#define ADC_ISR_OVW_Msk                   (0x40UL)                  /*!< OVW (Bitfield-Mask: 0x01)                             */
#define ADC_ISR_WDTR_Pos                  (5UL)                     /*!< WDTR (Bit 5)                                          */
#define ADC_ISR_WDTR_Msk                  (0x20UL)                  /*!< WDTR (Bitfield-Mask: 0x01)                            */
#define ADC_ISR_WDTH_Pos                  (4UL)                     /*!< WDTH (Bit 4)                                          */
#define ADC_ISR_WDTH_Msk                  (0x10UL)                  /*!< WDTH (Bitfield-Mask: 0x01)                            */
#define ADC_ISR_WDTL_Pos                  (3UL)                     /*!< WDTL (Bit 3)                                          */
#define ADC_ISR_WDTL_Msk                  (0x8UL)                   /*!< WDTL (Bitfield-Mask: 0x01)                            */
#define ADC_ISR_EOA_Pos                   (2UL)                     /*!< EOA (Bit 2)                                           */
#define ADC_ISR_EOA_Msk                   (0x4UL)                   /*!< EOA (Bitfield-Mask: 0x01)                             */
#define ADC_ISR_EOS_Pos                   (1UL)                     /*!< EOS (Bit 1)                                           */
#define ADC_ISR_EOS_Msk                   (0x2UL)                   /*!< EOS (Bitfield-Mask: 0x01)                             */
#define ADC_ISR_EOC_Pos                   (0UL)                     /*!< EOC (Bit 0)                                           */
#define ADC_ISR_EOC_Msk                   (0x1UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define ADC_ICR_OVW_Pos                   (6UL)                     /*!< OVW (Bit 6)                                           */
#define ADC_ICR_OVW_Msk                   (0x40UL)                  /*!< OVW (Bitfield-Mask: 0x01)                             */
#define ADC_ICR_WDTR_Pos                  (5UL)                     /*!< WDTR (Bit 5)                                          */
#define ADC_ICR_WDTR_Msk                  (0x20UL)                  /*!< WDTR (Bitfield-Mask: 0x01)                            */
#define ADC_ICR_WDTH_Pos                  (4UL)                     /*!< WDTH (Bit 4)                                          */
#define ADC_ICR_WDTH_Msk                  (0x10UL)                  /*!< WDTH (Bitfield-Mask: 0x01)                            */
#define ADC_ICR_WDTL_Pos                  (3UL)                     /*!< WDTL (Bit 3)                                          */
#define ADC_ICR_WDTL_Msk                  (0x8UL)                   /*!< WDTL (Bitfield-Mask: 0x01)                            */
#define ADC_ICR_EOA_Pos                   (2UL)                     /*!< EOA (Bit 2)                                           */
#define ADC_ICR_EOA_Msk                   (0x4UL)                   /*!< EOA (Bitfield-Mask: 0x01)                             */
#define ADC_ICR_EOS_Pos                   (1UL)                     /*!< EOS (Bit 1)                                           */
#define ADC_ICR_EOS_Msk                   (0x2UL)                   /*!< EOS (Bitfield-Mask: 0x01)                             */
#define ADC_ICR_EOC_Pos                   (0UL)                     /*!< EOC (Bit 0)                                           */
#define ADC_ICR_EOC_Msk                   (0x1UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
/* =======================================================  RESULT140  ======================================================= */
#define ADC_RESULT140_RESULT_Pos          (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULT140_RESULT_Msk          (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* =======================================================  RESULT141  ======================================================= */
#define ADC_RESULT141_RESULT_Pos          (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULT141_RESULT_Msk          (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* =======================================================  RESULT142  ======================================================= */
#define ADC_RESULT142_RESULT_Pos          (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULT142_RESULT_Msk          (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* =======================================================  RESULT143  ======================================================= */
#define ADC_RESULT143_RESULT_Pos          (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADC_RESULT143_RESULT_Msk          (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* =======================================================  ENABLE14  ======================================================== */
#define ADC_ENABLE14_KEY_Pos              (0UL)                     /*!< KEY (Bit 0)                                           */
#define ADC_ENABLE14_KEY_Msk              (0xffffUL)                /*!< KEY (Bitfield-Mask: 0xffff)                           */


/* =========================================================================================================================== */
/* ================                                           ATIM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ARR  ========================================================== */
#define ATIM_ARR_ARR_Pos                  (0UL)                     /*!< ARR (Bit 0)                                           */
#define ATIM_ARR_ARR_Msk                  (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CNT  ========================================================== */
#define ATIM_CNT_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define ATIM_CNT_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CR  =========================================================== */
#define ATIM_CR_UNDE_Pos                  (29UL)                    /*!< UNDE (Bit 29)                                         */
#define ATIM_CR_UNDE_Msk                  (0x20000000UL)            /*!< UNDE (Bitfield-Mask: 0x01)                            */
#define ATIM_CR_OVE_Pos                   (28UL)                    /*!< OVE (Bit 28)                                          */
#define ATIM_CR_OVE_Msk                   (0x10000000UL)            /*!< OVE (Bitfield-Mask: 0x01)                             */
#define ATIM_CR_DIR_Pos                   (27UL)                    /*!< DIR (Bit 27)                                          */
#define ATIM_CR_DIR_Msk                   (0x8000000UL)             /*!< DIR (Bitfield-Mask: 0x01)                             */
#define ATIM_CR_BG_Pos                    (26UL)                    /*!< BG (Bit 26)                                           */
#define ATIM_CR_BG_Msk                    (0x4000000UL)             /*!< BG (Bitfield-Mask: 0x01)                              */
#define ATIM_CR_UG_Pos                    (25UL)                    /*!< UG (Bit 25)                                           */
#define ATIM_CR_UG_Msk                    (0x2000000UL)             /*!< UG (Bitfield-Mask: 0x01)                              */
#define ATIM_CR_TG_Pos                    (24UL)                    /*!< TG (Bit 24)                                           */
#define ATIM_CR_TG_Msk                    (0x1000000UL)             /*!< TG (Bitfield-Mask: 0x01)                              */
#define ATIM_CR_OCCE_Pos                  (23UL)                    /*!< OCCE (Bit 23)                                         */
#define ATIM_CR_OCCE_Msk                  (0x800000UL)              /*!< OCCE (Bitfield-Mask: 0x01)                            */
#define ATIM_CR_CISA_Pos                  (21UL)                    /*!< CISA (Bit 21)                                         */
#define ATIM_CR_CISA_Msk                  (0x600000UL)              /*!< CISA (Bitfield-Mask: 0x03)                            */
#define ATIM_CR_BIE_Pos                   (20UL)                    /*!< BIE (Bit 20)                                          */
#define ATIM_CR_BIE_Msk                   (0x100000UL)              /*!< BIE (Bitfield-Mask: 0x01)                             */
#define ATIM_CR_TIE_Pos                   (19UL)                    /*!< TIE (Bit 19)                                          */
#define ATIM_CR_TIE_Msk                   (0x80000UL)               /*!< TIE (Bitfield-Mask: 0x01)                             */
#define ATIM_CR_URS_Pos                   (17UL)                    /*!< URS (Bit 17)                                          */
#define ATIM_CR_URS_Msk                   (0x20000UL)               /*!< URS (Bitfield-Mask: 0x01)                             */
#define ATIM_CR_OCCS_Pos                  (16UL)                    /*!< OCCS (Bit 16)                                         */
#define ATIM_CR_OCCS_Msk                  (0x10000UL)               /*!< OCCS (Bitfield-Mask: 0x01)                            */
#define ATIM_CR_ONESHOT_Pos               (14UL)                    /*!< ONESHOT (Bit 14)                                      */
#define ATIM_CR_ONESHOT_Msk               (0x4000UL)                /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
#define ATIM_CR_MODE_Pos                  (12UL)                    /*!< MODE (Bit 12)                                         */
#define ATIM_CR_MODE_Msk                  (0x3000UL)                /*!< MODE (Bitfield-Mask: 0x03)                            */
#define ATIM_CR_UIE_Pos                   (10UL)                    /*!< UIE (Bit 10)                                          */
#define ATIM_CR_UIE_Msk                   (0x400UL)                 /*!< UIE (Bitfield-Mask: 0x01)                             */
#define ATIM_CR_BUFPEN_Pos                (7UL)                     /*!< BUFPEN (Bit 7)                                        */
#define ATIM_CR_BUFPEN_Msk                (0x80UL)                  /*!< BUFPEN (Bitfield-Mask: 0x01)                          */
#define ATIM_CR_PRS_Pos                   (4UL)                     /*!< PRS (Bit 4)                                           */
#define ATIM_CR_PRS_Msk                   (0x70UL)                  /*!< PRS (Bitfield-Mask: 0x07)                             */
#define ATIM_CR_PWM2S_Pos                 (3UL)                     /*!< PWM2S (Bit 3)                                         */
#define ATIM_CR_PWM2S_Msk                 (0x8UL)                   /*!< PWM2S (Bitfield-Mask: 0x01)                           */
#define ATIM_CR_CT_Pos                    (2UL)                     /*!< CT (Bit 2)                                            */
#define ATIM_CR_CT_Msk                    (0x4UL)                   /*!< CT (Bitfield-Mask: 0x01)                              */
#define ATIM_CR_COMP_Pos                  (1UL)                     /*!< COMP (Bit 1)                                          */
#define ATIM_CR_COMP_Msk                  (0x2UL)                   /*!< COMP (Bitfield-Mask: 0x01)                            */
#define ATIM_CR_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define ATIM_CR_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ISR  ========================================================== */
#define ATIM_ISR_C4AF_Pos                 (18UL)                    /*!< C4AF (Bit 18)                                         */
#define ATIM_ISR_C4AF_Msk                 (0x40000UL)               /*!< C4AF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_UNDF_Pos                 (17UL)                    /*!< UNDF (Bit 17)                                         */
#define ATIM_ISR_UNDF_Msk                 (0x20000UL)               /*!< UNDF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_OVF_Pos                  (16UL)                    /*!< OVF (Bit 16)                                          */
#define ATIM_ISR_OVF_Msk                  (0x10000UL)               /*!< OVF (Bitfield-Mask: 0x01)                             */
#define ATIM_ISR_TIF_Pos                  (15UL)                    /*!< TIF (Bit 15)                                          */
#define ATIM_ISR_TIF_Msk                  (0x8000UL)                /*!< TIF (Bitfield-Mask: 0x01)                             */
#define ATIM_ISR_BIF_Pos                  (14UL)                    /*!< BIF (Bit 14)                                          */
#define ATIM_ISR_BIF_Msk                  (0x4000UL)                /*!< BIF (Bitfield-Mask: 0x01)                             */
#define ATIM_ISR_C3BE_Pos                 (13UL)                    /*!< C3BE (Bit 13)                                         */
#define ATIM_ISR_C3BE_Msk                 (0x2000UL)                /*!< C3BE (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C2BE_Pos                 (12UL)                    /*!< C2BE (Bit 12)                                         */
#define ATIM_ISR_C2BE_Msk                 (0x1000UL)                /*!< C2BE (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C1BE_Pos                 (11UL)                    /*!< C1BE (Bit 11)                                         */
#define ATIM_ISR_C1BE_Msk                 (0x800UL)                 /*!< C1BE (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C3AE_Pos                 (10UL)                    /*!< C3AE (Bit 10)                                         */
#define ATIM_ISR_C3AE_Msk                 (0x400UL)                 /*!< C3AE (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C2AE_Pos                 (9UL)                     /*!< C2AE (Bit 9)                                          */
#define ATIM_ISR_C2AE_Msk                 (0x200UL)                 /*!< C2AE (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C1AE_Pos                 (8UL)                     /*!< C1AE (Bit 8)                                          */
#define ATIM_ISR_C1AE_Msk                 (0x100UL)                 /*!< C1AE (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C3BF_Pos                 (7UL)                     /*!< C3BF (Bit 7)                                          */
#define ATIM_ISR_C3BF_Msk                 (0x80UL)                  /*!< C3BF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C2BF_Pos                 (6UL)                     /*!< C2BF (Bit 6)                                          */
#define ATIM_ISR_C2BF_Msk                 (0x40UL)                  /*!< C2BF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C1BF_Pos                 (5UL)                     /*!< C1BF (Bit 5)                                          */
#define ATIM_ISR_C1BF_Msk                 (0x20UL)                  /*!< C1BF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C3AF_Pos                 (4UL)                     /*!< C3AF (Bit 4)                                          */
#define ATIM_ISR_C3AF_Msk                 (0x10UL)                  /*!< C3AF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C2AF_Pos                 (3UL)                     /*!< C2AF (Bit 3)                                          */
#define ATIM_ISR_C2AF_Msk                 (0x8UL)                   /*!< C2AF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_C1AF_Pos                 (2UL)                     /*!< C1AF (Bit 2)                                          */
#define ATIM_ISR_C1AF_Msk                 (0x4UL)                   /*!< C1AF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_UIF_Pos                  (0UL)                     /*!< UIF (Bit 0)                                           */
#define ATIM_ISR_UIF_Msk                  (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define ATIM_ICR_C4AF_Pos                 (18UL)                    /*!< C4AF (Bit 18)                                         */
#define ATIM_ICR_C4AF_Msk                 (0x40000UL)               /*!< C4AF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_UNDF_Pos                 (17UL)                    /*!< UNDF (Bit 17)                                         */
#define ATIM_ICR_UNDF_Msk                 (0x20000UL)               /*!< UNDF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_OVF_Pos                  (16UL)                    /*!< OVF (Bit 16)                                          */
#define ATIM_ICR_OVF_Msk                  (0x10000UL)               /*!< OVF (Bitfield-Mask: 0x01)                             */
#define ATIM_ICR_TIF_Pos                  (15UL)                    /*!< TIF (Bit 15)                                          */
#define ATIM_ICR_TIF_Msk                  (0x8000UL)                /*!< TIF (Bitfield-Mask: 0x01)                             */
#define ATIM_ICR_BIF_Pos                  (14UL)                    /*!< BIF (Bit 14)                                          */
#define ATIM_ICR_BIF_Msk                  (0x4000UL)                /*!< BIF (Bitfield-Mask: 0x01)                             */
#define ATIM_ICR_C3BE_Pos                 (13UL)                    /*!< C3BE (Bit 13)                                         */
#define ATIM_ICR_C3BE_Msk                 (0x2000UL)                /*!< C3BE (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C2BE_Pos                 (12UL)                    /*!< C2BE (Bit 12)                                         */
#define ATIM_ICR_C2BE_Msk                 (0x1000UL)                /*!< C2BE (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C1BE_Pos                 (11UL)                    /*!< C1BE (Bit 11)                                         */
#define ATIM_ICR_C1BE_Msk                 (0x800UL)                 /*!< C1BE (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C3AE_Pos                 (10UL)                    /*!< C3AE (Bit 10)                                         */
#define ATIM_ICR_C3AE_Msk                 (0x400UL)                 /*!< C3AE (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C2AE_Pos                 (9UL)                     /*!< C2AE (Bit 9)                                          */
#define ATIM_ICR_C2AE_Msk                 (0x200UL)                 /*!< C2AE (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C1AE_Pos                 (8UL)                     /*!< C1AE (Bit 8)                                          */
#define ATIM_ICR_C1AE_Msk                 (0x100UL)                 /*!< C1AE (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C3BF_Pos                 (7UL)                     /*!< C3BF (Bit 7)                                          */
#define ATIM_ICR_C3BF_Msk                 (0x80UL)                  /*!< C3BF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C2BF_Pos                 (6UL)                     /*!< C2BF (Bit 6)                                          */
#define ATIM_ICR_C2BF_Msk                 (0x40UL)                  /*!< C2BF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C1BF_Pos                 (5UL)                     /*!< C1BF (Bit 5)                                          */
#define ATIM_ICR_C1BF_Msk                 (0x20UL)                  /*!< C1BF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C3AF_Pos                 (4UL)                     /*!< C3AF (Bit 4)                                          */
#define ATIM_ICR_C3AF_Msk                 (0x10UL)                  /*!< C3AF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C2AF_Pos                 (3UL)                     /*!< C2AF (Bit 3)                                          */
#define ATIM_ICR_C2AF_Msk                 (0x8UL)                   /*!< C2AF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_C1AF_Pos                 (2UL)                     /*!< C1AF (Bit 2)                                          */
#define ATIM_ICR_C1AF_Msk                 (0x4UL)                   /*!< C1AF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_UIF_Pos                  (0UL)                     /*!< UIF (Bit 0)                                           */
#define ATIM_ICR_UIF_Msk                  (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* =========================================================  MSCR  ========================================================== */
#define ATIM_MSCR_IB1S_Pos                (12UL)                    /*!< IB1S (Bit 12)                                         */
#define ATIM_MSCR_IB1S_Msk                (0x1000UL)                /*!< IB1S (Bitfield-Mask: 0x01)                            */
#define ATIM_MSCR_IA1S_Pos                (11UL)                    /*!< IA1S (Bit 11)                                         */
#define ATIM_MSCR_IA1S_Msk                (0x800UL)                 /*!< IA1S (Bitfield-Mask: 0x01)                            */
#define ATIM_MSCR_SMS_Pos                 (8UL)                     /*!< SMS (Bit 8)                                           */
#define ATIM_MSCR_SMS_Msk                 (0x700UL)                 /*!< SMS (Bitfield-Mask: 0x07)                             */
#define ATIM_MSCR_TS_Pos                  (5UL)                     /*!< TS (Bit 5)                                            */
#define ATIM_MSCR_TS_Msk                  (0xe0UL)                  /*!< TS (Bitfield-Mask: 0x07)                              */
#define ATIM_MSCR_CCDS_Pos                (3UL)                     /*!< CCDS (Bit 3)                                          */
#define ATIM_MSCR_CCDS_Msk                (0x8UL)                   /*!< CCDS (Bitfield-Mask: 0x01)                            */
#define ATIM_MSCR_MMS_Pos                 (0UL)                     /*!< MMS (Bit 0)                                           */
#define ATIM_MSCR_MMS_Msk                 (0x7UL)                   /*!< MMS (Bitfield-Mask: 0x07)                             */
/* =========================================================  FLTR  ========================================================== */
#define ATIM_FLTR_ETP_Pos                 (31UL)                    /*!< ETP (Bit 31)                                          */
#define ATIM_FLTR_ETP_Msk                 (0x80000000UL)            /*!< ETP (Bitfield-Mask: 0x01)                             */
#define ATIM_FLTR_FLTET_Pos               (28UL)                    /*!< FLTET (Bit 28)                                        */
#define ATIM_FLTR_FLTET_Msk               (0x70000000UL)            /*!< FLTET (Bitfield-Mask: 0x07)                           */
#define ATIM_FLTR_BKP_Pos                 (27UL)                    /*!< BKP (Bit 27)                                          */
#define ATIM_FLTR_BKP_Msk                 (0x8000000UL)             /*!< BKP (Bitfield-Mask: 0x01)                             */
#define ATIM_FLTR_FLTBK_Pos               (24UL)                    /*!< FLTBK (Bit 24)                                        */
#define ATIM_FLTR_FLTBK_Msk               (0x7000000UL)             /*!< FLTBK (Bitfield-Mask: 0x07)                           */
#define ATIM_FLTR_CCP3B_Pos               (23UL)                    /*!< CCP3B (Bit 23)                                        */
#define ATIM_FLTR_CCP3B_Msk               (0x800000UL)              /*!< CCP3B (Bitfield-Mask: 0x01)                           */
#define ATIM_FLTR_OCM3BFLT3B_Pos          (20UL)                    /*!< OCM3BFLT3B (Bit 20)                                   */
#define ATIM_FLTR_OCM3BFLT3B_Msk          (0x700000UL)              /*!< OCM3BFLT3B (Bitfield-Mask: 0x07)                      */
#define ATIM_FLTR_CCP3A_Pos               (19UL)                    /*!< CCP3A (Bit 19)                                        */
#define ATIM_FLTR_CCP3A_Msk               (0x80000UL)               /*!< CCP3A (Bitfield-Mask: 0x01)                           */
#define ATIM_FLTR_OCM3AFLT3A_Pos          (16UL)                    /*!< OCM3AFLT3A (Bit 16)                                   */
#define ATIM_FLTR_OCM3AFLT3A_Msk          (0x70000UL)               /*!< OCM3AFLT3A (Bitfield-Mask: 0x07)                      */
#define ATIM_FLTR_CCP2B_Pos               (15UL)                    /*!< CCP2B (Bit 15)                                        */
#define ATIM_FLTR_CCP2B_Msk               (0x8000UL)                /*!< CCP2B (Bitfield-Mask: 0x01)                           */
#define ATIM_FLTR_OCM2BFLT2B_Pos          (12UL)                    /*!< OCM2BFLT2B (Bit 12)                                   */
#define ATIM_FLTR_OCM2BFLT2B_Msk          (0x7000UL)                /*!< OCM2BFLT2B (Bitfield-Mask: 0x07)                      */
#define ATIM_FLTR_CCP2A_Pos               (11UL)                    /*!< CCP2A (Bit 11)                                        */
#define ATIM_FLTR_CCP2A_Msk               (0x800UL)                 /*!< CCP2A (Bitfield-Mask: 0x01)                           */
#define ATIM_FLTR_OCM2AFLT2A_Pos          (8UL)                     /*!< OCM2AFLT2A (Bit 8)                                    */
#define ATIM_FLTR_OCM2AFLT2A_Msk          (0x700UL)                 /*!< OCM2AFLT2A (Bitfield-Mask: 0x07)                      */
#define ATIM_FLTR_CCP1B_Pos               (7UL)                     /*!< CCP1B (Bit 7)                                         */
#define ATIM_FLTR_CCP1B_Msk               (0x80UL)                  /*!< CCP1B (Bitfield-Mask: 0x01)                           */
#define ATIM_FLTR_OCM1BFLT1B_Pos          (4UL)                     /*!< OCM1BFLT1B (Bit 4)                                    */
#define ATIM_FLTR_OCM1BFLT1B_Msk          (0x70UL)                  /*!< OCM1BFLT1B (Bitfield-Mask: 0x07)                      */
#define ATIM_FLTR_CCP1A_Pos               (3UL)                     /*!< CCP1A (Bit 3)                                         */
#define ATIM_FLTR_CCP1A_Msk               (0x8UL)                   /*!< CCP1A (Bitfield-Mask: 0x01)                           */
#define ATIM_FLTR_OCM1AFLT1A_Pos          (0UL)                     /*!< OCM1AFLT1A (Bit 0)                                    */
#define ATIM_FLTR_OCM1AFLT1A_Msk          (0x7UL)                   /*!< OCM1AFLT1A (Bitfield-Mask: 0x07)                      */
/* =========================================================  TRIG  ========================================================== */
#define ATIM_TRIG_ADTE_Pos                (7UL)                     /*!< ADTE (Bit 7)                                          */
#define ATIM_TRIG_ADTE_Msk                (0x80UL)                  /*!< ADTE (Bitfield-Mask: 0x01)                            */
#define ATIM_TRIG_CM3BE_Pos               (6UL)                     /*!< CM3BE (Bit 6)                                         */
#define ATIM_TRIG_CM3BE_Msk               (0x40UL)                  /*!< CM3BE (Bitfield-Mask: 0x01)                           */
#define ATIM_TRIG_CM2BE_Pos               (5UL)                     /*!< CM2BE (Bit 5)                                         */
#define ATIM_TRIG_CM2BE_Msk               (0x20UL)                  /*!< CM2BE (Bitfield-Mask: 0x01)                           */
#define ATIM_TRIG_CM1BE_Pos               (4UL)                     /*!< CM1BE (Bit 4)                                         */
#define ATIM_TRIG_CM1BE_Msk               (0x10UL)                  /*!< CM1BE (Bitfield-Mask: 0x01)                           */
#define ATIM_TRIG_CM3AE_Pos               (3UL)                     /*!< CM3AE (Bit 3)                                         */
#define ATIM_TRIG_CM3AE_Msk               (0x8UL)                   /*!< CM3AE (Bitfield-Mask: 0x01)                           */
#define ATIM_TRIG_CM2AE_Pos               (2UL)                     /*!< CM2AE (Bit 2)                                         */
#define ATIM_TRIG_CM2AE_Msk               (0x4UL)                   /*!< CM2AE (Bitfield-Mask: 0x01)                           */
#define ATIM_TRIG_CM1AE_Pos               (1UL)                     /*!< CM1AE (Bit 1)                                         */
#define ATIM_TRIG_CM1AE_Msk               (0x2UL)                   /*!< CM1AE (Bitfield-Mask: 0x01)                           */
#define ATIM_TRIG_UEVE_Pos                (0UL)                     /*!< UEVE (Bit 0)                                          */
#define ATIM_TRIG_UEVE_Msk                (0x1UL)                   /*!< UEVE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CH1CR  ========================================================= */
#define ATIM_CH1CR_CCGB_Pos               (15UL)                    /*!< CCGB (Bit 15)                                         */
#define ATIM_CH1CR_CCGB_Msk               (0x8000UL)                /*!< CCGB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH1CR_CCGA_Pos               (14UL)                    /*!< CCGA (Bit 14)                                         */
#define ATIM_CH1CR_CCGA_Msk               (0x4000UL)                /*!< CCGA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH1CR_CISB_Pos               (12UL)                    /*!< CISB (Bit 12)                                         */
#define ATIM_CH1CR_CISB_Msk               (0x3000UL)                /*!< CISB (Bitfield-Mask: 0x03)                            */
#define ATIM_CH1CR_CDEB_Pos               (11UL)                    /*!< CDEB (Bit 11)                                         */
#define ATIM_CH1CR_CDEB_Msk               (0x800UL)                 /*!< CDEB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH1CR_CDEA_Pos               (10UL)                    /*!< CDEA (Bit 10)                                         */
#define ATIM_CH1CR_CDEA_Msk               (0x400UL)                 /*!< CDEA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH1CR_CIEB_Pos               (9UL)                     /*!< CIEB (Bit 9)                                          */
#define ATIM_CH1CR_CIEB_Msk               (0x200UL)                 /*!< CIEB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH1CR_CIEA_Pos               (8UL)                     /*!< CIEA (Bit 8)                                          */
#define ATIM_CH1CR_CIEA_Msk               (0x100UL)                 /*!< CIEA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH1CR_BUFEB_Pos              (7UL)                     /*!< BUFEB (Bit 7)                                         */
#define ATIM_CH1CR_BUFEB_Msk              (0x80UL)                  /*!< BUFEB (Bitfield-Mask: 0x01)                           */
#define ATIM_CH1CR_BUFEA_Pos              (6UL)                     /*!< BUFEA (Bit 6)                                         */
#define ATIM_CH1CR_BUFEA_Msk              (0x40UL)                  /*!< BUFEA (Bitfield-Mask: 0x01)                           */
#define ATIM_CH1CR_CSB_Pos                (5UL)                     /*!< CSB (Bit 5)                                           */
#define ATIM_CH1CR_CSB_Msk                (0x20UL)                  /*!< CSB (Bitfield-Mask: 0x01)                             */
#define ATIM_CH1CR_CSA_Pos                (4UL)                     /*!< CSA (Bit 4)                                           */
#define ATIM_CH1CR_CSA_Msk                (0x10UL)                  /*!< CSA (Bitfield-Mask: 0x01)                             */
#define ATIM_CH1CR_BKSB_Pos               (2UL)                     /*!< BKSB (Bit 2)                                          */
#define ATIM_CH1CR_BKSB_Msk               (0xcUL)                   /*!< BKSB (Bitfield-Mask: 0x03)                            */
#define ATIM_CH1CR_BKSA_Pos               (0UL)                     /*!< BKSA (Bit 0)                                          */
#define ATIM_CH1CR_BKSA_Msk               (0x3UL)                   /*!< BKSA (Bitfield-Mask: 0x03)                            */
/* =========================================================  CH2CR  ========================================================= */
#define ATIM_CH2CR_CCGB_Pos               (15UL)                    /*!< CCGB (Bit 15)                                         */
#define ATIM_CH2CR_CCGB_Msk               (0x8000UL)                /*!< CCGB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH2CR_CCGA_Pos               (14UL)                    /*!< CCGA (Bit 14)                                         */
#define ATIM_CH2CR_CCGA_Msk               (0x4000UL)                /*!< CCGA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH2CR_CISB_Pos               (12UL)                    /*!< CISB (Bit 12)                                         */
#define ATIM_CH2CR_CISB_Msk               (0x3000UL)                /*!< CISB (Bitfield-Mask: 0x03)                            */
#define ATIM_CH2CR_CDEB_Pos               (11UL)                    /*!< CDEB (Bit 11)                                         */
#define ATIM_CH2CR_CDEB_Msk               (0x800UL)                 /*!< CDEB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH2CR_CDEA_Pos               (10UL)                    /*!< CDEA (Bit 10)                                         */
#define ATIM_CH2CR_CDEA_Msk               (0x400UL)                 /*!< CDEA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH2CR_CIEB_Pos               (9UL)                     /*!< CIEB (Bit 9)                                          */
#define ATIM_CH2CR_CIEB_Msk               (0x200UL)                 /*!< CIEB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH2CR_CIEA_Pos               (8UL)                     /*!< CIEA (Bit 8)                                          */
#define ATIM_CH2CR_CIEA_Msk               (0x100UL)                 /*!< CIEA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH2CR_BUFEB_Pos              (7UL)                     /*!< BUFEB (Bit 7)                                         */
#define ATIM_CH2CR_BUFEB_Msk              (0x80UL)                  /*!< BUFEB (Bitfield-Mask: 0x01)                           */
#define ATIM_CH2CR_BUFEA_Pos              (6UL)                     /*!< BUFEA (Bit 6)                                         */
#define ATIM_CH2CR_BUFEA_Msk              (0x40UL)                  /*!< BUFEA (Bitfield-Mask: 0x01)                           */
#define ATIM_CH2CR_CSB_Pos                (5UL)                     /*!< CSB (Bit 5)                                           */
#define ATIM_CH2CR_CSB_Msk                (0x20UL)                  /*!< CSB (Bitfield-Mask: 0x01)                             */
#define ATIM_CH2CR_CSA_Pos                (4UL)                     /*!< CSA (Bit 4)                                           */
#define ATIM_CH2CR_CSA_Msk                (0x10UL)                  /*!< CSA (Bitfield-Mask: 0x01)                             */
#define ATIM_CH2CR_BKSB_Pos               (2UL)                     /*!< BKSB (Bit 2)                                          */
#define ATIM_CH2CR_BKSB_Msk               (0xcUL)                   /*!< BKSB (Bitfield-Mask: 0x03)                            */
#define ATIM_CH2CR_BKSA_Pos               (0UL)                     /*!< BKSA (Bit 0)                                          */
#define ATIM_CH2CR_BKSA_Msk               (0x3UL)                   /*!< BKSA (Bitfield-Mask: 0x03)                            */
/* =========================================================  CH3CR  ========================================================= */
#define ATIM_CH3CR_CCGB_Pos               (15UL)                    /*!< CCGB (Bit 15)                                         */
#define ATIM_CH3CR_CCGB_Msk               (0x8000UL)                /*!< CCGB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH3CR_CCGA_Pos               (14UL)                    /*!< CCGA (Bit 14)                                         */
#define ATIM_CH3CR_CCGA_Msk               (0x4000UL)                /*!< CCGA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH3CR_CISB_Pos               (12UL)                    /*!< CISB (Bit 12)                                         */
#define ATIM_CH3CR_CISB_Msk               (0x3000UL)                /*!< CISB (Bitfield-Mask: 0x03)                            */
#define ATIM_CH3CR_CDEB_Pos               (11UL)                    /*!< CDEB (Bit 11)                                         */
#define ATIM_CH3CR_CDEB_Msk               (0x800UL)                 /*!< CDEB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH3CR_CDEA_Pos               (10UL)                    /*!< CDEA (Bit 10)                                         */
#define ATIM_CH3CR_CDEA_Msk               (0x400UL)                 /*!< CDEA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH3CR_CIEB_Pos               (9UL)                     /*!< CIEB (Bit 9)                                          */
#define ATIM_CH3CR_CIEB_Msk               (0x200UL)                 /*!< CIEB (Bitfield-Mask: 0x01)                            */
#define ATIM_CH3CR_CIEA_Pos               (8UL)                     /*!< CIEA (Bit 8)                                          */
#define ATIM_CH3CR_CIEA_Msk               (0x100UL)                 /*!< CIEA (Bitfield-Mask: 0x01)                            */
#define ATIM_CH3CR_BUFEB_Pos              (7UL)                     /*!< BUFEB (Bit 7)                                         */
#define ATIM_CH3CR_BUFEB_Msk              (0x80UL)                  /*!< BUFEB (Bitfield-Mask: 0x01)                           */
#define ATIM_CH3CR_BUFEA_Pos              (6UL)                     /*!< BUFEA (Bit 6)                                         */
#define ATIM_CH3CR_BUFEA_Msk              (0x40UL)                  /*!< BUFEA (Bitfield-Mask: 0x01)                           */
#define ATIM_CH3CR_CSB_Pos                (5UL)                     /*!< CSB (Bit 5)                                           */
#define ATIM_CH3CR_CSB_Msk                (0x20UL)                  /*!< CSB (Bitfield-Mask: 0x01)                             */
#define ATIM_CH3CR_CSA_Pos                (4UL)                     /*!< CSA (Bit 4)                                           */
#define ATIM_CH3CR_CSA_Msk                (0x10UL)                  /*!< CSA (Bitfield-Mask: 0x01)                             */
#define ATIM_CH3CR_BKSB_Pos               (2UL)                     /*!< BKSB (Bit 2)                                          */
#define ATIM_CH3CR_BKSB_Msk               (0xcUL)                   /*!< BKSB (Bitfield-Mask: 0x03)                            */
#define ATIM_CH3CR_BKSA_Pos               (0UL)                     /*!< BKSA (Bit 0)                                          */
#define ATIM_CH3CR_BKSA_Msk               (0x3UL)                   /*!< BKSA (Bitfield-Mask: 0x03)                            */
/* =========================================================  CH4CR  ========================================================= */
#define ATIM_CH4CR_C4EN_Pos               (5UL)                     /*!< C4EN (Bit 5)                                          */
#define ATIM_CH4CR_C4EN_Msk               (0x20UL)                  /*!< C4EN (Bitfield-Mask: 0x01)                            */
#define ATIM_CH4CR_CIS_Pos                (3UL)                     /*!< CIS (Bit 3)                                           */
#define ATIM_CH4CR_CIS_Msk                (0x18UL)                  /*!< CIS (Bitfield-Mask: 0x03)                             */
#define ATIM_CH4CR_CDE_Pos                (2UL)                     /*!< CDE (Bit 2)                                           */
#define ATIM_CH4CR_CDE_Msk                (0x4UL)                   /*!< CDE (Bitfield-Mask: 0x01)                             */
#define ATIM_CH4CR_CIE_Pos                (1UL)                     /*!< CIE (Bit 1)                                           */
#define ATIM_CH4CR_CIE_Msk                (0x2UL)                   /*!< CIE (Bitfield-Mask: 0x01)                             */
#define ATIM_CH4CR_BUFE_Pos               (0UL)                     /*!< BUFE (Bit 0)                                          */
#define ATIM_CH4CR_BUFE_Msk               (0x1UL)                   /*!< BUFE (Bitfield-Mask: 0x01)                            */
/* ==========================================================  DTR  ========================================================== */
#define ATIM_DTR_VCE_Pos                  (14UL)                    /*!< VCE (Bit 14)                                          */
#define ATIM_DTR_VCE_Msk                  (0x4000UL)                /*!< VCE (Bitfield-Mask: 0x01)                             */
#define ATIM_DTR_SAFEEN_Pos               (13UL)                    /*!< SAFEEN (Bit 13)                                       */
#define ATIM_DTR_SAFEEN_Msk               (0x2000UL)                /*!< SAFEEN (Bitfield-Mask: 0x01)                          */
#define ATIM_DTR_MOE_Pos                  (12UL)                    /*!< MOE (Bit 12)                                          */
#define ATIM_DTR_MOE_Msk                  (0x1000UL)                /*!< MOE (Bitfield-Mask: 0x01)                             */
#define ATIM_DTR_AOE_Pos                  (11UL)                    /*!< AOE (Bit 11)                                          */
#define ATIM_DTR_AOE_Msk                  (0x800UL)                 /*!< AOE (Bitfield-Mask: 0x01)                             */
#define ATIM_DTR_BKE_Pos                  (10UL)                    /*!< BKE (Bit 10)                                          */
#define ATIM_DTR_BKE_Msk                  (0x400UL)                 /*!< BKE (Bitfield-Mask: 0x01)                             */
#define ATIM_DTR_DTEN_Pos                 (9UL)                     /*!< DTEN (Bit 9)                                          */
#define ATIM_DTR_DTEN_Msk                 (0x200UL)                 /*!< DTEN (Bitfield-Mask: 0x01)                            */
#define ATIM_DTR_DTR_Pos                  (0UL)                     /*!< DTR (Bit 0)                                           */
#define ATIM_DTR_DTR_Msk                  (0xffUL)                  /*!< DTR (Bitfield-Mask: 0xff)                             */
/* ==========================================================  RCR  ========================================================== */
#define ATIM_RCR_UD_Pos                   (9UL)                     /*!< UD (Bit 9)                                            */
#define ATIM_RCR_UD_Msk                   (0x200UL)                 /*!< UD (Bitfield-Mask: 0x01)                              */
#define ATIM_RCR_OV_Pos                   (8UL)                     /*!< OV (Bit 8)                                            */
#define ATIM_RCR_OV_Msk                   (0x100UL)                 /*!< OV (Bitfield-Mask: 0x01)                              */
#define ATIM_RCR_RCR_Pos                  (0UL)                     /*!< RCR (Bit 0)                                           */
#define ATIM_RCR_RCR_Msk                  (0xffUL)                  /*!< RCR (Bitfield-Mask: 0xff)                             */
/* ========================================================  CH1CCRA  ======================================================== */
#define ATIM_CH1CCRA_CCR1A_Pos            (0UL)                     /*!< CCR1A (Bit 0)                                         */
#define ATIM_CH1CCRA_CCR1A_Msk            (0xffffUL)                /*!< CCR1A (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH1CCRB  ======================================================== */
#define ATIM_CH1CCRB_CCR1B_Pos            (0UL)                     /*!< CCR1B (Bit 0)                                         */
#define ATIM_CH1CCRB_CCR1B_Msk            (0xffffUL)                /*!< CCR1B (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH2CCRA  ======================================================== */
#define ATIM_CH2CCRA_CCR2A_Pos            (0UL)                     /*!< CCR2A (Bit 0)                                         */
#define ATIM_CH2CCRA_CCR2A_Msk            (0xffffUL)                /*!< CCR2A (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH2CCRB  ======================================================== */
#define ATIM_CH2CCRB_CCR2B_Pos            (0UL)                     /*!< CCR2B (Bit 0)                                         */
#define ATIM_CH2CCRB_CCR2B_Msk            (0xffffUL)                /*!< CCR2B (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH3CCRA  ======================================================== */
#define ATIM_CH3CCRA_CCR3A_Pos            (0UL)                     /*!< CCR3A (Bit 0)                                         */
#define ATIM_CH3CCRA_CCR3A_Msk            (0xffffUL)                /*!< CCR3A (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH3CCRB  ======================================================== */
#define ATIM_CH3CCRB_CCR3B_Pos            (0UL)                     /*!< CCR3B (Bit 0)                                         */
#define ATIM_CH3CCRB_CCR3B_Msk            (0xffffUL)                /*!< CCR3B (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH4CCR  ========================================================= */
#define ATIM_CH4CCR_CCR4_Pos              (0UL)                     /*!< CCR4 (Bit 0)                                          */
#define ATIM_CH4CCR_CCR4_Msk              (0xffffUL)                /*!< CCR4 (Bitfield-Mask: 0xffff)                          */


/* =========================================================================================================================== */
/* ================                                            AWT                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define AWT_CR_SRC_Pos                    (8UL)                     /*!< SRC (Bit 8)                                           */
#define AWT_CR_SRC_Msk                    (0x700UL)                 /*!< SRC (Bitfield-Mask: 0x07)                             */
#define AWT_CR_PRS_Pos                    (4UL)                     /*!< PRS (Bit 4)                                           */
#define AWT_CR_PRS_Msk                    (0xf0UL)                  /*!< PRS (Bitfield-Mask: 0x0f)                             */
#define AWT_CR_MD_Pos                     (1UL)                     /*!< MD (Bit 1)                                            */
#define AWT_CR_MD_Msk                     (0x6UL)                   /*!< MD (Bitfield-Mask: 0x03)                              */
#define AWT_CR_EN_Pos                     (0UL)                     /*!< EN (Bit 0)                                            */
#define AWT_CR_EN_Msk                     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ARR  ========================================================== */
#define AWT_ARR_ARR_Pos                   (0UL)                     /*!< ARR (Bit 0)                                           */
#define AWT_ARR_ARR_Msk                   (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CNT  ========================================================== */
#define AWT_CNT_CNT_Pos                   (0UL)                     /*!< CNT (Bit 0)                                           */
#define AWT_CNT_CNT_Msk                   (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  IER  ========================================================== */
#define AWT_IER_UD_Pos                    (3UL)                     /*!< UD (Bit 3)                                            */
#define AWT_IER_UD_Msk                    (0x8UL)                   /*!< UD (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ISR  ========================================================== */
#define AWT_ISR_UD_Pos                    (3UL)                     /*!< UD (Bit 3)                                            */
#define AWT_ISR_UD_Msk                    (0x8UL)                   /*!< UD (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ICR  ========================================================== */
#define AWT_ICR_UD_Pos                    (3UL)                     /*!< UD (Bit 3)                                            */
#define AWT_ICR_UD_Msk                    (0x8UL)                   /*!< UD (Bitfield-Mask: 0x01)                              */


/* =========================================================================================================================== */
/* ================                                           BTIM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ARR  ========================================================== */
#define BTIMx_ARR_ARR_Pos                 (0UL)                     /*!< ARR (Bit 0)                                           */
#define BTIMx_ARR_ARR_Msk                 (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CNT  ========================================================== */
#define BTIMx_CNT_CNT_Pos                 (0UL)                     /*!< CNT (Bit 0)                                           */
#define BTIMx_CNT_CNT_Msk                 (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ACR  ========================================================== */
#define BTIMx_ACR_ETRFLT_Pos              (4UL)                     /*!< ETRFLT (Bit 4)                                        */
#define BTIMx_ACR_ETRFLT_Msk              (0x70UL)                  /*!< ETRFLT (Bitfield-Mask: 0x07)                          */
/* ==========================================================  BCR  ========================================================== */
#define BTIMx_BCR_PRSSTATUS_Pos           (11UL)                    /*!< PRSSTATUS (Bit 11)                                    */
#define BTIMx_BCR_PRSSTATUS_Msk           (0x7800UL)                /*!< PRSSTATUS (Bitfield-Mask: 0x0f)                       */
#define BTIMx_BCR_PRS_Pos                 (7UL)                     /*!< PRS (Bit 7)                                           */
#define BTIMx_BCR_PRS_Msk                 (0x780UL)                 /*!< PRS (Bitfield-Mask: 0x0f)                             */
#define BTIMx_BCR_TOGEN_Pos               (6UL)                     /*!< TOGEN (Bit 6)                                         */
#define BTIMx_BCR_TOGEN_Msk               (0x40UL)                  /*!< TOGEN (Bitfield-Mask: 0x01)                           */
#define BTIMx_BCR_ONESHOT_Pos             (5UL)                     /*!< ONESHOT (Bit 5)                                       */
#define BTIMx_BCR_ONESHOT_Msk             (0x20UL)                  /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
#define BTIMx_BCR_POL_Pos                 (4UL)                     /*!< POL (Bit 4)                                           */
#define BTIMx_BCR_POL_Msk                 (0x10UL)                  /*!< POL (Bitfield-Mask: 0x01)                             */
#define BTIMx_BCR_TRS_Pos                 (3UL)                     /*!< TRS (Bit 3)                                           */
#define BTIMx_BCR_TRS_Msk                 (0x8UL)                   /*!< TRS (Bitfield-Mask: 0x01)                             */
#define BTIMx_BCR_MODE_Pos                (1UL)                     /*!< MODE (Bit 1)                                          */
#define BTIMx_BCR_MODE_Msk                (0x6UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
#define BTIMx_BCR_EN_Pos                  (0UL)                     /*!< EN (Bit 0)                                            */
#define BTIMx_BCR_EN_Msk                  (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  IER  ========================================================== */
#define BTIMx_IER_TOP_Pos                 (2UL)                     /*!< TOP (Bit 2)                                           */
#define BTIMx_IER_TOP_Msk                 (0x4UL)                   /*!< TOP (Bitfield-Mask: 0x01)                             */
#define BTIMx_IER_TI_Pos                  (1UL)                     /*!< TI (Bit 1)                                            */
#define BTIMx_IER_TI_Msk                  (0x2UL)                   /*!< TI (Bitfield-Mask: 0x01)                              */
#define BTIMx_IER_OV_Pos                  (0UL)                     /*!< OV (Bit 0)                                            */
#define BTIMx_IER_OV_Msk                  (0x1UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ISR  ========================================================== */
#define BTIMx_ISR_TOP_Pos                 (2UL)                     /*!< TOP (Bit 2)                                           */
#define BTIMx_ISR_TOP_Msk                 (0x4UL)                   /*!< TOP (Bitfield-Mask: 0x01)                             */
#define BTIMx_ISR_TI_Pos                  (1UL)                     /*!< TI (Bit 1)                                            */
#define BTIMx_ISR_TI_Msk                  (0x2UL)                   /*!< TI (Bitfield-Mask: 0x01)                              */
#define BTIMx_ISR_OV_Pos                  (0UL)                     /*!< OV (Bit 0)                                            */
#define BTIMx_ISR_OV_Msk                  (0x1UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ICR  ========================================================== */
#define BTIMx_ICR_TOP_Pos                 (2UL)                     /*!< TOP (Bit 2)                                           */
#define BTIMx_ICR_TOP_Msk                 (0x4UL)                   /*!< TOP (Bitfield-Mask: 0x01)                             */
#define BTIMx_ICR_TI_Pos                  (1UL)                     /*!< TI (Bit 1)                                            */
#define BTIMx_ICR_TI_Msk                  (0x2UL)                   /*!< TI (Bitfield-Mask: 0x01)                              */
#define BTIMx_ICR_OV_Pos                  (0UL)                     /*!< OV (Bit 0)                                            */
#define BTIMx_ICR_OV_Msk                  (0x1UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
/* ==========================================================  DMA  ========================================================== */
#define BTIMx_DMA_TRS_Pos                 (1UL)                     /*!< TRS (Bit 1)                                           */
#define BTIMx_DMA_TRS_Msk                 (0x2UL)                   /*!< TRS (Bitfield-Mask: 0x01)                             */
#define BTIMx_DMA_OV_Pos                  (0UL)                     /*!< OV (Bit 0)                                            */
#define BTIMx_DMA_OV_Msk                  (0x1UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */


/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define CRC_CR_MODE_Pos                   (0UL)                     /*!< MODE (Bit 0)                                          */
#define CRC_CR_MODE_Msk                   (0xfUL)                   /*!< MODE (Bitfield-Mask: 0x0f)                            */
/* =========================================================  DR32  ========================================================== */
#define CRC_DR32_DR32_Pos                 (0UL)                     /*!< DR32 (Bit 0)                                          */
#define CRC_DR32_DR32_Msk                 (0xffffffffUL)            /*!< DR32 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DR16  ========================================================== */
#define CRC_DR16_DR16_Pos                 (0UL)                     /*!< DR16 (Bit 0)                                          */
#define CRC_DR16_DR16_Msk                 (0xffffUL)                /*!< DR16 (Bitfield-Mask: 0xffff)                          */
/* ==========================================================  DR8  ========================================================== */
#define CRC_DR8_DR8_Pos                   (0UL)                     /*!< DR8 (Bit 0)                                           */
#define CRC_DR8_DR8_Msk                   (0xffUL)                  /*!< DR8 (Bitfield-Mask: 0xff)                             */
/* =======================================================  RESULT32  ======================================================== */
#define CRC_RESULT32_RESULT32_Pos         (0UL)                     /*!< RESULT32 (Bit 0)                                      */
#define CRC_RESULT32_RESULT32_Msk         (0xffffffffUL)            /*!< RESULT32 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  RESULT16  ======================================================== */
#define CRC_RESULT16_RESULT16_Pos         (0UL)                     /*!< RESULT16 (Bit 0)                                      */
#define CRC_RESULT16_RESULT16_Msk         (0xffffUL)                /*!< RESULT16 (Bitfield-Mask: 0xffff)                      */


/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ISR  ========================================================== */
#define DMA_ISR_TE5_Pos                   (17UL)                    /*!< TE5 (Bit 17)                                          */
#define DMA_ISR_TE5_Msk                   (0x20000UL)               /*!< TE5 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC5_Pos                   (16UL)                    /*!< TC5 (Bit 16)                                          */
#define DMA_ISR_TC5_Msk                   (0x10000UL)               /*!< TC5 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TE4_Pos                   (13UL)                    /*!< TE4 (Bit 13)                                          */
#define DMA_ISR_TE4_Msk                   (0x2000UL)                /*!< TE4 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC4_Pos                   (12UL)                    /*!< TC4 (Bit 12)                                          */
#define DMA_ISR_TC4_Msk                   (0x1000UL)                /*!< TC4 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TE3_Pos                   (9UL)                     /*!< TE3 (Bit 9)                                           */
#define DMA_ISR_TE3_Msk                   (0x200UL)                 /*!< TE3 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC3_Pos                   (8UL)                     /*!< TC3 (Bit 8)                                           */
#define DMA_ISR_TC3_Msk                   (0x100UL)                 /*!< TC3 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TE2_Pos                   (5UL)                     /*!< TE2 (Bit 5)                                           */
#define DMA_ISR_TE2_Msk                   (0x20UL)                  /*!< TE2 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC2_Pos                   (4UL)                     /*!< TC2 (Bit 4)                                           */
#define DMA_ISR_TC2_Msk                   (0x10UL)                  /*!< TC2 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TE1_Pos                   (1UL)                     /*!< TE1 (Bit 1)                                           */
#define DMA_ISR_TE1_Msk                   (0x2UL)                   /*!< TE1 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC1_Pos                   (0UL)                     /*!< TC1 (Bit 0)                                           */
#define DMA_ISR_TC1_Msk                   (0x1UL)                   /*!< TC1 (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define DMA_ICR_TE5_Pos                   (17UL)                    /*!< TE5 (Bit 17)                                          */
#define DMA_ICR_TE5_Msk                   (0x20000UL)               /*!< TE5 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC5_Pos                   (16UL)                    /*!< TC5 (Bit 16)                                          */
#define DMA_ICR_TC5_Msk                   (0x10000UL)               /*!< TC5 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TE4_Pos                   (13UL)                    /*!< TE4 (Bit 13)                                          */
#define DMA_ICR_TE4_Msk                   (0x2000UL)                /*!< TE4 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC4_Pos                   (12UL)                    /*!< TC4 (Bit 12)                                          */
#define DMA_ICR_TC4_Msk                   (0x1000UL)                /*!< TC4 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TE3_Pos                   (9UL)                     /*!< TE3 (Bit 9)                                           */
#define DMA_ICR_TE3_Msk                   (0x200UL)                 /*!< TE3 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC3_Pos                   (8UL)                     /*!< TC3 (Bit 8)                                           */
#define DMA_ICR_TC3_Msk                   (0x100UL)                 /*!< TC3 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TE2_Pos                   (5UL)                     /*!< TE2 (Bit 5)                                           */
#define DMA_ICR_TE2_Msk                   (0x20UL)                  /*!< TE2 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC2_Pos                   (4UL)                     /*!< TC2 (Bit 4)                                           */
#define DMA_ICR_TC2_Msk                   (0x10UL)                  /*!< TC2 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TE1_Pos                   (1UL)                     /*!< TE1 (Bit 1)                                           */
#define DMA_ICR_TE1_Msk                   (0x2UL)                   /*!< TE1 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC1_Pos                   (0UL)                     /*!< TC1 (Bit 0)                                           */
#define DMA_ICR_TC1_Msk                   (0x1UL)                   /*!< TC1 (Bitfield-Mask: 0x01)                             */
/* =========================================================  CSR1  ========================================================== */
#define DMA_CSR1_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR1_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR1_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR1_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR1_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR1_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR1_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR1_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR1_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR1_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR1_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR1_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR1_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR1_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR1_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR1_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  CNT1  ========================================================== */
#define DMA_CNT1_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT1_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT1_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT1_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR1  ======================================================== */
#define DMA_SRCADDR1_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR1_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR1  ======================================================== */
#define DMA_DSTADDR1_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR1_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG1  ========================================================= */
#define DMA_TRIG1_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG1_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG1_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG1_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG1_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG1_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CSR2  ========================================================== */
#define DMA_CSR2_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR2_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR2_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR2_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR2_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR2_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR2_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR2_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR2_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR2_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR2_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR2_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR2_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR2_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR2_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR2_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  CNT2  ========================================================== */
#define DMA_CNT2_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT2_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT2_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT2_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR2  ======================================================== */
#define DMA_SRCADDR2_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR2_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR2  ======================================================== */
#define DMA_DSTADDR2_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR2_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG2  ========================================================= */
#define DMA_TRIG2_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG2_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG2_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG2_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG2_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG2_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CSR3  ========================================================== */
#define DMA_CSR3_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR3_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR3_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR3_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR3_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR3_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR3_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR3_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR3_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR3_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR3_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR3_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR3_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR3_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR3_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR3_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  CNT3  ========================================================== */
#define DMA_CNT3_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT3_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT3_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT3_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR3  ======================================================== */
#define DMA_SRCADDR3_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR3_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR3  ======================================================== */
#define DMA_DSTADDR3_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR3_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG3  ========================================================= */
#define DMA_TRIG3_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG3_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG3_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG3_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG3_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG3_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CSR4  ========================================================== */
#define DMA_CSR4_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR4_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR4_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR4_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR4_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR4_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR4_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR4_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR4_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR4_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR4_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR4_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR4_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR4_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR4_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR4_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  CNT4  ========================================================== */
#define DMA_CNT4_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT4_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT4_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT4_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR4  ======================================================== */
#define DMA_SRCADDR4_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR4_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR4  ======================================================== */
#define DMA_DSTADDR4_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR4_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG4  ========================================================= */
#define DMA_TRIG4_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG4_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG4_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG4_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG4_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG4_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CSR5  ========================================================== */
#define DMA_CSR5_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR5_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR5_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR5_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR5_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR5_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR5_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR5_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR5_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR5_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR5_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR5_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR5_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR5_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR5_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR5_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  CNT5  ========================================================== */
#define DMA_CNT5_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT5_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT5_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT5_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR5  ======================================================== */
#define DMA_SRCADDR5_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR5_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR5  ======================================================== */
#define DMA_DSTADDR5_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR5_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG5  ========================================================= */
#define DMA_TRIG5_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG5_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG5_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG5_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG5_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG5_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                        DMACHANNEL                                         ================ */
/* =========================================================================================================================== */

/* ==========================================================  CSR  ========================================================== */
#define DMACHx_CSR_STATUS_Pos        (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMACHx_CSR_STATUS_Msk        (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMACHx_CSR_SIZE_Pos          (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMACHx_CSR_SIZE_Msk          (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMACHx_CSR_DSTINC_Pos        (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMACHx_CSR_DSTINC_Msk        (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMACHx_CSR_SRCINC_Pos        (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMACHx_CSR_SRCINC_Msk        (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMACHx_CSR_TRANS_Pos         (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMACHx_CSR_TRANS_Msk         (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMACHx_CSR_TEIE_Pos          (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMACHx_CSR_TEIE_Msk          (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMACHx_CSR_TCIE_Pos          (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMACHx_CSR_TCIE_Msk          (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMACHx_CSR_EN_Pos            (0UL)                     /*!< EN (Bit 0)                                            */
#define DMACHx_CSR_EN_Msk            (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CNT  ========================================================== */
#define DMACHx_CNT_REPEAT_Pos        (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMACHx_CNT_REPEAT_Msk        (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMACHx_CNT_CNT_Pos           (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMACHx_CNT_CNT_Msk           (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ========================================================  SRCADDR  ======================================================== */
#define DMACHx_SRCADDR_SRCADDR_Pos   (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMACHx_SRCADDR_SRCADDR_Msk   (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DSTADDR  ======================================================== */
#define DMACHx_DSTADDR_DSTADDR_Pos   (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMACHx_DSTADDR_DSTADDR_Msk   (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG  ========================================================== */
#define DMACHx_TRIG_HARDSRC_Pos      (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMACHx_TRIG_HARDSRC_Msk      (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMACHx_TRIG_SOFTSRC_Pos      (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMACHx_TRIG_SOFTSRC_Msk      (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMACHx_TRIG_TYPE_Pos         (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMACHx_TRIG_TYPE_Msk         (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define FLASH_CR1_KEY_Pos                 (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_CR1_KEY_Msk                 (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_CR1_SECURITY_Pos            (6UL)                     /*!< SECURITY (Bit 6)                                      */
#define FLASH_CR1_SECURITY_Msk            (0xc0UL)                  /*!< SECURITY (Bitfield-Mask: 0x03)                        */
#define FLASH_CR1_BUSY_Pos                (5UL)                     /*!< BUSY (Bit 5)                                          */
#define FLASH_CR1_BUSY_Msk                (0x20UL)                  /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define FLASH_CR1_STANDBY_Pos             (4UL)                     /*!< STANDBY (Bit 4)                                       */
#define FLASH_CR1_STANDBY_Msk             (0x10UL)                  /*!< STANDBY (Bitfield-Mask: 0x01)                         */
#define FLASH_CR1_MODE_Pos                (0UL)                     /*!< MODE (Bit 0)                                          */
#define FLASH_CR1_MODE_Msk                (0x3UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
/* ==========================================================  CR2  ========================================================== */
#define FLASH_CR2_KEY_Pos                 (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_CR2_KEY_Msk                 (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_CR2_CACHE_Pos               (4UL)                     /*!< CACHE (Bit 4)                                         */
#define FLASH_CR2_CACHE_Msk               (0x10UL)                  /*!< CACHE (Bitfield-Mask: 0x01)                           */
#define FLASH_CR2_FETCH_Pos               (3UL)                     /*!< FETCH (Bit 3)                                         */
#define FLASH_CR2_FETCH_Msk               (0x8UL)                   /*!< FETCH (Bitfield-Mask: 0x01)                           */
#define FLASH_CR2_WAIT_Pos                (0UL)                     /*!< WAIT (Bit 0)                                          */
#define FLASH_CR2_WAIT_Msk                (0x7UL)                   /*!< WAIT (Bitfield-Mask: 0x07)                            */
/* =======================================================  PAGELOCK  ======================================================== */
#define FLASH_PAGELOCK_KEY_Pos            (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_PAGELOCK_KEY_Msk            (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_PAGELOCK_LOCK15_Pos         (15UL)                    /*!< LOCK15 (Bit 15)                                       */
#define FLASH_PAGELOCK_LOCK15_Msk         (0x8000UL)                /*!< LOCK15 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK14_Pos         (14UL)                    /*!< LOCK14 (Bit 14)                                       */
#define FLASH_PAGELOCK_LOCK14_Msk         (0x4000UL)                /*!< LOCK14 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK13_Pos         (13UL)                    /*!< LOCK13 (Bit 13)                                       */
#define FLASH_PAGELOCK_LOCK13_Msk         (0x2000UL)                /*!< LOCK13 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK12_Pos         (12UL)                    /*!< LOCK12 (Bit 12)                                       */
#define FLASH_PAGELOCK_LOCK12_Msk         (0x1000UL)                /*!< LOCK12 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK11_Pos         (11UL)                    /*!< LOCK11 (Bit 11)                                       */
#define FLASH_PAGELOCK_LOCK11_Msk         (0x800UL)                 /*!< LOCK11 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK10_Pos         (10UL)                    /*!< LOCK10 (Bit 10)                                       */
#define FLASH_PAGELOCK_LOCK10_Msk         (0x400UL)                 /*!< LOCK10 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK9_Pos          (9UL)                     /*!< LOCK9 (Bit 9)                                         */
#define FLASH_PAGELOCK_LOCK9_Msk          (0x200UL)                 /*!< LOCK9 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK8_Pos          (8UL)                     /*!< LOCK8 (Bit 8)                                         */
#define FLASH_PAGELOCK_LOCK8_Msk          (0x100UL)                 /*!< LOCK8 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK7_Pos          (7UL)                     /*!< LOCK7 (Bit 7)                                         */
#define FLASH_PAGELOCK_LOCK7_Msk          (0x80UL)                  /*!< LOCK7 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK6_Pos          (6UL)                     /*!< LOCK6 (Bit 6)                                         */
#define FLASH_PAGELOCK_LOCK6_Msk          (0x40UL)                  /*!< LOCK6 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK5_Pos          (5UL)                     /*!< LOCK5 (Bit 5)                                         */
#define FLASH_PAGELOCK_LOCK5_Msk          (0x20UL)                  /*!< LOCK5 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK4_Pos          (4UL)                     /*!< LOCK4 (Bit 4)                                         */
#define FLASH_PAGELOCK_LOCK4_Msk          (0x10UL)                  /*!< LOCK4 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK3_Pos          (3UL)                     /*!< LOCK3 (Bit 3)                                         */
#define FLASH_PAGELOCK_LOCK3_Msk          (0x8UL)                   /*!< LOCK3 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK2_Pos          (2UL)                     /*!< LOCK2 (Bit 2)                                         */
#define FLASH_PAGELOCK_LOCK2_Msk          (0x4UL)                   /*!< LOCK2 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK1_Pos          (1UL)                     /*!< LOCK1 (Bit 1)                                         */
#define FLASH_PAGELOCK_LOCK1_Msk          (0x2UL)                   /*!< LOCK1 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK0_Pos          (0UL)                     /*!< LOCK0 (Bit 0)                                         */
#define FLASH_PAGELOCK_LOCK0_Msk          (0x1UL)                   /*!< LOCK0 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  IER  ========================================================== */
#define FLASH_IER_PROG_Pos                (4UL)                     /*!< PROG (Bit 4)                                          */
#define FLASH_IER_PROG_Msk                (0x10UL)                  /*!< PROG (Bitfield-Mask: 0x01)                            */
#define FLASH_IER_PAGELOCK_Pos            (1UL)                     /*!< PAGELOCK (Bit 1)                                      */
#define FLASH_IER_PAGELOCK_Msk            (0x2UL)                   /*!< PAGELOCK (Bitfield-Mask: 0x01)                        */
#define FLASH_IER_PC_Pos                  (0UL)                     /*!< PC (Bit 0)                                            */
#define FLASH_IER_PC_Msk                  (0x1UL)                   /*!< PC (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ISR  ========================================================== */
#define FLASH_ISR_PROG_Pos                (4UL)                     /*!< PROG (Bit 4)                                          */
#define FLASH_ISR_PROG_Msk                (0x10UL)                  /*!< PROG (Bitfield-Mask: 0x01)                            */
#define FLASH_ISR_PAGELOCK_Pos            (1UL)                     /*!< PAGELOCK (Bit 1)                                      */
#define FLASH_ISR_PAGELOCK_Msk            (0x2UL)                   /*!< PAGELOCK (Bitfield-Mask: 0x01)                        */
#define FLASH_ISR_PC_Pos                  (0UL)                     /*!< PC (Bit 0)                                            */
#define FLASH_ISR_PC_Msk                  (0x1UL)                   /*!< PC (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ICR  ========================================================== */
#define FLASH_ICR_PROG_Pos                (4UL)                     /*!< PROG (Bit 4)                                          */
#define FLASH_ICR_PROG_Msk                (0x10UL)                  /*!< PROG (Bitfield-Mask: 0x01)                            */
#define FLASH_ICR_PAGELOCK_Pos            (1UL)                     /*!< PAGELOCK (Bit 1)                                      */
#define FLASH_ICR_PAGELOCK_Msk            (0x2UL)                   /*!< PAGELOCK (Bitfield-Mask: 0x01)                        */
#define FLASH_ICR_PC_Pos                  (0UL)                     /*!< PC (Bit 0)                                            */
#define FLASH_ICR_PC_Msk                  (0x1UL)                   /*!< PC (Bitfield-Mask: 0x01)                              */


/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  DIR  ========================================================== */
#define GPIOx_DIR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_DIR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_DIR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_DIR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_DIR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_DIR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_DIR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_DIR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_DIR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_DIR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_DIR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_DIR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_DIR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_DIR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_DIR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_DIR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_DIR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =======================================================  OPENDRAIN  ======================================================= */
#define GPIOx_OPENDRAIN_PIN15_Pos         (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_OPENDRAIN_PIN15_Msk         (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN14_Pos         (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_OPENDRAIN_PIN14_Msk         (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN13_Pos         (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_OPENDRAIN_PIN13_Msk         (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN12_Pos         (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_OPENDRAIN_PIN12_Msk         (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN11_Pos         (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_OPENDRAIN_PIN11_Msk         (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN10_Pos         (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_OPENDRAIN_PIN10_Msk         (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN9_Pos          (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_OPENDRAIN_PIN9_Msk          (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN8_Pos          (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_OPENDRAIN_PIN8_Msk          (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN7_Pos          (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_OPENDRAIN_PIN7_Msk          (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN6_Pos          (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_OPENDRAIN_PIN6_Msk          (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN5_Pos          (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_OPENDRAIN_PIN5_Msk          (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN4_Pos          (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_OPENDRAIN_PIN4_Msk          (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN3_Pos          (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_OPENDRAIN_PIN3_Msk          (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN2_Pos          (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_OPENDRAIN_PIN2_Msk          (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN1_Pos          (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_OPENDRAIN_PIN1_Msk          (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN0_Pos          (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_OPENDRAIN_PIN0_Msk          (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  SPEED  ========================================================= */
#define GPIOx_SPEED_PIN15_Pos             (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_SPEED_PIN15_Msk             (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_SPEED_PIN14_Pos             (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_SPEED_PIN14_Msk             (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_SPEED_PIN13_Pos             (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_SPEED_PIN13_Msk             (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_SPEED_PIN12_Pos             (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_SPEED_PIN12_Msk             (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_SPEED_PIN11_Pos             (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_SPEED_PIN11_Msk             (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_SPEED_PIN10_Pos             (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_SPEED_PIN10_Msk             (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_SPEED_PIN9_Pos              (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_SPEED_PIN9_Msk              (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN8_Pos              (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_SPEED_PIN8_Msk              (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN7_Pos              (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_SPEED_PIN7_Msk              (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN6_Pos              (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_SPEED_PIN6_Msk              (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN5_Pos              (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_SPEED_PIN5_Msk              (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN4_Pos              (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_SPEED_PIN4_Msk              (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN3_Pos              (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_SPEED_PIN3_Msk              (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN2_Pos              (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_SPEED_PIN2_Msk              (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN1_Pos              (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_SPEED_PIN1_Msk              (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_SPEED_PIN0_Pos              (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_SPEED_PIN0_Msk              (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  PDR  ========================================================== */
#define GPIOx_PDR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_PDR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PDR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_PDR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PDR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_PDR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PDR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_PDR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PDR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_PDR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PDR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_PDR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PDR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_PDR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_PDR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_PDR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_PDR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_PDR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_PDR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_PDR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_PDR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_PDR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PDR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_PDR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  PUR  ========================================================== */
#define GPIOx_PUR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_PUR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_PUR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_PUR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_PUR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_PUR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_PUR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_PUR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_PUR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_PUR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_PUR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_PUR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_PUR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_PUR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_PUR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_PUR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_PUR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  AFRH  ========================================================== */
#define GPIOx_AFRH_AFR15_Pos              (28UL)                    /*!< AFR15 (Bit 28)                                        */
#define GPIOx_AFRH_AFR15_Msk              (0xf0000000UL)            /*!< AFR15 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_AFR14_Pos              (24UL)                    /*!< AFR14 (Bit 24)                                        */
#define GPIOx_AFRH_AFR14_Msk              (0xf000000UL)             /*!< AFR14 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_AFR13_Pos              (20UL)                    /*!< AFR13 (Bit 20)                                        */
#define GPIOx_AFRH_AFR13_Msk              (0xf00000UL)              /*!< AFR13 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_AFR12_Pos              (16UL)                    /*!< AFR12 (Bit 16)                                        */
#define GPIOx_AFRH_AFR12_Msk              (0xf0000UL)               /*!< AFR12 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_AFR11_Pos              (12UL)                    /*!< AFR11 (Bit 12)                                        */
#define GPIOx_AFRH_AFR11_Msk              (0xf000UL)                /*!< AFR11 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_AFR10_Pos              (8UL)                     /*!< AFR10 (Bit 8)                                         */
#define GPIOx_AFRH_AFR10_Msk              (0xf00UL)                 /*!< AFR10 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_AFR9_Pos               (4UL)                     /*!< AFR9 (Bit 4)                                          */
#define GPIOx_AFRH_AFR9_Msk               (0xf0UL)                  /*!< AFR9 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRH_AFR8_Pos               (0UL)                     /*!< AFR8 (Bit 0)                                          */
#define GPIOx_AFRH_AFR8_Msk               (0xfUL)                   /*!< AFR8 (Bitfield-Mask: 0x0f)                            */
/* =========================================================  AFRL  ========================================================== */
#define GPIOx_AFRL_AFR7_Pos               (28UL)                    /*!< AFR7 (Bit 28)                                         */
#define GPIOx_AFRL_AFR7_Msk               (0xf0000000UL)            /*!< AFR7 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_AFR6_Pos               (24UL)                    /*!< AFR6 (Bit 24)                                         */
#define GPIOx_AFRL_AFR6_Msk               (0xf000000UL)             /*!< AFR6 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_AFR5_Pos               (20UL)                    /*!< AFR5 (Bit 20)                                         */
#define GPIOx_AFRL_AFR5_Msk               (0xf00000UL)              /*!< AFR5 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_AFR4_Pos               (16UL)                    /*!< AFR4 (Bit 16)                                         */
#define GPIOx_AFRL_AFR4_Msk               (0xf0000UL)               /*!< AFR4 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_AFR3_Pos               (12UL)                    /*!< AFR3 (Bit 12)                                         */
#define GPIOx_AFRL_AFR3_Msk               (0xf000UL)                /*!< AFR3 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_AFR2_Pos               (8UL)                     /*!< AFR2 (Bit 8)                                          */
#define GPIOx_AFRL_AFR2_Msk               (0xf00UL)                 /*!< AFR2 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_AFR1_Pos               (4UL)                     /*!< AFR1 (Bit 4)                                          */
#define GPIOx_AFRL_AFR1_Msk               (0xf0UL)                  /*!< AFR1 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_AFR0_Pos               (0UL)                     /*!< AFR0 (Bit 0)                                          */
#define GPIOx_AFRL_AFR0_Msk               (0xfUL)                   /*!< AFR0 (Bitfield-Mask: 0x0f)                            */
/* ========================================================  ANALOG  ========================================================= */
#define GPIOx_ANALOG_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_ANALOG_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_ANALOG_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_ANALOG_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_ANALOG_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_ANALOG_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_ANALOG_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_ANALOG_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_ANALOG_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_ANALOG_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_ANALOG_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_ANALOG_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_ANALOG_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_ANALOG_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_ANALOG_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_ANALOG_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_ANALOG_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  DRIVER  ========================================================= */
#define GPIOx_DRIVER_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_DRIVER_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DRIVER_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_DRIVER_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DRIVER_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_DRIVER_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DRIVER_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_DRIVER_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DRIVER_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_DRIVER_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DRIVER_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_DRIVER_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DRIVER_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_DRIVER_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_DRIVER_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_DRIVER_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_DRIVER_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_DRIVER_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_DRIVER_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_DRIVER_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_DRIVER_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_DRIVER_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DRIVER_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_DRIVER_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  RISEIE  ========================================================= */
#define GPIOx_RISEIE_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_RISEIE_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_RISEIE_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_RISEIE_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_RISEIE_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_RISEIE_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_RISEIE_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_RISEIE_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_RISEIE_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_RISEIE_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_RISEIE_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_RISEIE_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_RISEIE_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_RISEIE_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_RISEIE_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_RISEIE_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_RISEIE_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  FALLIE  ========================================================= */
#define GPIOx_FALLIE_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_FALLIE_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_FALLIE_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_FALLIE_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_FALLIE_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_FALLIE_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_FALLIE_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_FALLIE_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_FALLIE_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_FALLIE_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_FALLIE_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_FALLIE_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_FALLIE_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_FALLIE_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_FALLIE_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_FALLIE_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_FALLIE_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  HIGHIE  ========================================================= */
#define GPIOx_HIGHIE_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_HIGHIE_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_HIGHIE_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_HIGHIE_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_HIGHIE_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_HIGHIE_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_HIGHIE_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_HIGHIE_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_HIGHIE_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_HIGHIE_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_HIGHIE_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_HIGHIE_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_HIGHIE_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_HIGHIE_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_HIGHIE_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_HIGHIE_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_HIGHIE_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_HIGHIE_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_HIGHIE_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_HIGHIE_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_HIGHIE_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_HIGHIE_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_HIGHIE_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_HIGHIE_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  LOWIE  ========================================================= */
#define GPIOx_LOWIE_PIN15_Pos             (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_LOWIE_PIN15_Msk             (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOWIE_PIN14_Pos             (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_LOWIE_PIN14_Msk             (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOWIE_PIN13_Pos             (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_LOWIE_PIN13_Msk             (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOWIE_PIN12_Pos             (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_LOWIE_PIN12_Msk             (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOWIE_PIN11_Pos             (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_LOWIE_PIN11_Msk             (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOWIE_PIN10_Pos             (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_LOWIE_PIN10_Msk             (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOWIE_PIN9_Pos              (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_LOWIE_PIN9_Msk              (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN8_Pos              (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_LOWIE_PIN8_Msk              (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN7_Pos              (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_LOWIE_PIN7_Msk              (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN6_Pos              (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_LOWIE_PIN6_Msk              (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN5_Pos              (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_LOWIE_PIN5_Msk              (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN4_Pos              (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_LOWIE_PIN4_Msk              (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN3_Pos              (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_LOWIE_PIN3_Msk              (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN2_Pos              (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_LOWIE_PIN2_Msk              (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN1_Pos              (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_LOWIE_PIN1_Msk              (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOWIE_PIN0_Pos              (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_LOWIE_PIN0_Msk              (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ISR  ========================================================== */
#define GPIOx_ISR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_ISR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_ISR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_ISR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_ISR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_ISR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_ISR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_ISR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_ISR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_ISR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_ISR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_ISR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_ISR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_ISR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_ISR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_ISR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_ISR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ICR  ========================================================== */
#define GPIOx_ICR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_ICR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_ICR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_ICR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_ICR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_ICR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_ICR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_ICR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_ICR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_ICR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_ICR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_ICR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_ICR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_ICR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_ICR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_ICR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_ICR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  LOCK  ========================================================== */
#define GPIOx_LOCK_KEY_Pos                (16UL)                    /*!< KEY (Bit 16)                                          */
#define GPIOx_LOCK_KEY_Msk                (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define GPIOx_LOCK_PIN15_Pos              (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_LOCK_PIN15_Msk              (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOCK_PIN14_Pos              (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_LOCK_PIN14_Msk              (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOCK_PIN13_Pos              (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_LOCK_PIN13_Msk              (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOCK_PIN12_Pos              (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_LOCK_PIN12_Msk              (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOCK_PIN11_Pos              (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_LOCK_PIN11_Msk              (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOCK_PIN10_Pos              (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_LOCK_PIN10_Msk              (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_LOCK_PIN9_Pos               (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_LOCK_PIN9_Msk               (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN8_Pos               (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_LOCK_PIN8_Msk               (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN7_Pos               (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_LOCK_PIN7_Msk               (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN6_Pos               (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_LOCK_PIN6_Msk               (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN5_Pos               (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_LOCK_PIN5_Msk               (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN4_Pos               (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_LOCK_PIN4_Msk               (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN3_Pos               (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_LOCK_PIN3_Msk               (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN2_Pos               (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_LOCK_PIN2_Msk               (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN1_Pos               (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_LOCK_PIN1_Msk               (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_LOCK_PIN0_Pos               (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_LOCK_PIN0_Msk               (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  FILTER  ========================================================= */
#define GPIOx_FILTER_FLTCLK_Pos           (16UL)                    /*!< FLTCLK (Bit 16)                                       */
#define GPIOx_FILTER_FLTCLK_Msk           (0x70000UL)               /*!< FLTCLK (Bitfield-Mask: 0x07)                          */
#define GPIOx_FILTER_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_FILTER_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_FILTER_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_FILTER_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_FILTER_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_FILTER_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_FILTER_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_FILTER_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_FILTER_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_FILTER_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_FILTER_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_FILTER_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_FILTER_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_FILTER_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_FILTER_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_FILTER_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_FILTER_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  IDR  ========================================================== */
#define GPIOx_IDR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_IDR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_IDR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_IDR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_IDR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_IDR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_IDR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_IDR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_IDR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_IDR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_IDR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_IDR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_IDR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_IDR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_IDR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_IDR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_IDR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ODR  ========================================================== */
#define GPIOx_ODR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_ODR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_ODR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_ODR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_ODR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_ODR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_ODR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_ODR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_ODR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_ODR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_ODR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_ODR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_ODR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_ODR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_ODR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_ODR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_ODR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ======================================================  ODRLOWBYTE  ======================================================= */
#define GPIOx_ODRLOWBYTE_LOWBYTE_Pos      (0UL)                     /*!< LOWBYTE (Bit 0)                                       */
#define GPIOx_ODRLOWBYTE_LOWBYTE_Msk      (0xffUL)                  /*!< LOWBYTE (Bitfield-Mask: 0xff)                         */
/* ======================================================  ODRHIGHBYTE  ====================================================== */
#define GPIOx_ODRHIGHBYTE_HIGHBYTE_Pos    (0UL)                     /*!< HIGHBYTE (Bit 0)                                      */
#define GPIOx_ODRHIGHBYTE_HIGHBYTE_Msk    (0xffUL)                  /*!< HIGHBYTE (Bitfield-Mask: 0xff)                        */
/* ==========================================================  BRR  ========================================================== */
#define GPIOx_BRR_BRR15_Pos               (15UL)                    /*!< BRR15 (Bit 15)                                        */
#define GPIOx_BRR_BRR15_Msk               (0x8000UL)                /*!< BRR15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR14_Pos               (14UL)                    /*!< BRR14 (Bit 14)                                        */
#define GPIOx_BRR_BRR14_Msk               (0x4000UL)                /*!< BRR14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR13_Pos               (13UL)                    /*!< BRR13 (Bit 13)                                        */
#define GPIOx_BRR_BRR13_Msk               (0x2000UL)                /*!< BRR13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR12_Pos               (12UL)                    /*!< BRR12 (Bit 12)                                        */
#define GPIOx_BRR_BRR12_Msk               (0x1000UL)                /*!< BRR12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR11_Pos               (11UL)                    /*!< BRR11 (Bit 11)                                        */
#define GPIOx_BRR_BRR11_Msk               (0x800UL)                 /*!< BRR11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR10_Pos               (10UL)                    /*!< BRR10 (Bit 10)                                        */
#define GPIOx_BRR_BRR10_Msk               (0x400UL)                 /*!< BRR10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR9_Pos                (9UL)                     /*!< BRR9 (Bit 9)                                          */
#define GPIOx_BRR_BRR9_Msk                (0x200UL)                 /*!< BRR9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR8_Pos                (8UL)                     /*!< BRR8 (Bit 8)                                          */
#define GPIOx_BRR_BRR8_Msk                (0x100UL)                 /*!< BRR8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR7_Pos                (7UL)                     /*!< BRR7 (Bit 7)                                          */
#define GPIOx_BRR_BRR7_Msk                (0x80UL)                  /*!< BRR7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR6_Pos                (6UL)                     /*!< BRR6 (Bit 6)                                          */
#define GPIOx_BRR_BRR6_Msk                (0x40UL)                  /*!< BRR6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR5_Pos                (5UL)                     /*!< BRR5 (Bit 5)                                          */
#define GPIOx_BRR_BRR5_Msk                (0x20UL)                  /*!< BRR5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR4_Pos                (4UL)                     /*!< BRR4 (Bit 4)                                          */
#define GPIOx_BRR_BRR4_Msk                (0x10UL)                  /*!< BRR4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR3_Pos                (3UL)                     /*!< BRR3 (Bit 3)                                          */
#define GPIOx_BRR_BRR3_Msk                (0x8UL)                   /*!< BRR3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR2_Pos                (2UL)                     /*!< BRR2 (Bit 2)                                          */
#define GPIOx_BRR_BRR2_Msk                (0x4UL)                   /*!< BRR2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR1_Pos                (1UL)                     /*!< BRR1 (Bit 1)                                          */
#define GPIOx_BRR_BRR1_Msk                (0x2UL)                   /*!< BRR1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR0_Pos                (0UL)                     /*!< BRR0 (Bit 0)                                          */
#define GPIOx_BRR_BRR0_Msk                (0x1UL)                   /*!< BRR0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  BSRR  ========================================================== */
#define GPIOx_BSRR_BRR15_Pos              (31UL)                    /*!< BRR15 (Bit 31)                                        */
#define GPIOx_BSRR_BRR15_Msk              (0x80000000UL)            /*!< BRR15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR14_Pos              (30UL)                    /*!< BRR14 (Bit 30)                                        */
#define GPIOx_BSRR_BRR14_Msk              (0x40000000UL)            /*!< BRR14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR13_Pos              (29UL)                    /*!< BRR13 (Bit 29)                                        */
#define GPIOx_BSRR_BRR13_Msk              (0x20000000UL)            /*!< BRR13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR12_Pos              (28UL)                    /*!< BRR12 (Bit 28)                                        */
#define GPIOx_BSRR_BRR12_Msk              (0x10000000UL)            /*!< BRR12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR11_Pos              (27UL)                    /*!< BRR11 (Bit 27)                                        */
#define GPIOx_BSRR_BRR11_Msk              (0x8000000UL)             /*!< BRR11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR10_Pos              (26UL)                    /*!< BRR10 (Bit 26)                                        */
#define GPIOx_BSRR_BRR10_Msk              (0x4000000UL)             /*!< BRR10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR9_Pos               (25UL)                    /*!< BRR9 (Bit 25)                                         */
#define GPIOx_BSRR_BRR9_Msk               (0x2000000UL)             /*!< BRR9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR8_Pos               (24UL)                    /*!< BRR8 (Bit 24)                                         */
#define GPIOx_BSRR_BRR8_Msk               (0x1000000UL)             /*!< BRR8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR7_Pos               (23UL)                    /*!< BRR7 (Bit 23)                                         */
#define GPIOx_BSRR_BRR7_Msk               (0x800000UL)              /*!< BRR7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR6_Pos               (22UL)                    /*!< BRR6 (Bit 22)                                         */
#define GPIOx_BSRR_BRR6_Msk               (0x400000UL)              /*!< BRR6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR5_Pos               (21UL)                    /*!< BRR5 (Bit 21)                                         */
#define GPIOx_BSRR_BRR5_Msk               (0x200000UL)              /*!< BRR5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR4_Pos               (20UL)                    /*!< BRR4 (Bit 20)                                         */
#define GPIOx_BSRR_BRR4_Msk               (0x100000UL)              /*!< BRR4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR3_Pos               (19UL)                    /*!< BRR3 (Bit 19)                                         */
#define GPIOx_BSRR_BRR3_Msk               (0x80000UL)               /*!< BRR3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR2_Pos               (18UL)                    /*!< BRR2 (Bit 18)                                         */
#define GPIOx_BSRR_BRR2_Msk               (0x40000UL)               /*!< BRR2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR1_Pos               (17UL)                    /*!< BRR1 (Bit 17)                                         */
#define GPIOx_BSRR_BRR1_Msk               (0x20000UL)               /*!< BRR1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR0_Pos               (16UL)                    /*!< BRR0 (Bit 16)                                         */
#define GPIOx_BSRR_BRR0_Msk               (0x10000UL)               /*!< BRR0 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS15_Pos              (15UL)                    /*!< BSS15 (Bit 15)                                        */
#define GPIOx_BSRR_BSS15_Msk              (0x8000UL)                /*!< BSS15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS14_Pos              (14UL)                    /*!< BSS14 (Bit 14)                                        */
#define GPIOx_BSRR_BSS14_Msk              (0x4000UL)                /*!< BSS14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS13_Pos              (13UL)                    /*!< BSS13 (Bit 13)                                        */
#define GPIOx_BSRR_BSS13_Msk              (0x2000UL)                /*!< BSS13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS12_Pos              (12UL)                    /*!< BSS12 (Bit 12)                                        */
#define GPIOx_BSRR_BSS12_Msk              (0x1000UL)                /*!< BSS12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS11_Pos              (11UL)                    /*!< BSS11 (Bit 11)                                        */
#define GPIOx_BSRR_BSS11_Msk              (0x800UL)                 /*!< BSS11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS10_Pos              (10UL)                    /*!< BSS10 (Bit 10)                                        */
#define GPIOx_BSRR_BSS10_Msk              (0x400UL)                 /*!< BSS10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS9_Pos               (9UL)                     /*!< BSS9 (Bit 9)                                          */
#define GPIOx_BSRR_BSS9_Msk               (0x200UL)                 /*!< BSS9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS8_Pos               (8UL)                     /*!< BSS8 (Bit 8)                                          */
#define GPIOx_BSRR_BSS8_Msk               (0x100UL)                 /*!< BSS8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS7_Pos               (7UL)                     /*!< BSS7 (Bit 7)                                          */
#define GPIOx_BSRR_BSS7_Msk               (0x80UL)                  /*!< BSS7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS6_Pos               (6UL)                     /*!< BSS6 (Bit 6)                                          */
#define GPIOx_BSRR_BSS6_Msk               (0x40UL)                  /*!< BSS6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS5_Pos               (5UL)                     /*!< BSS5 (Bit 5)                                          */
#define GPIOx_BSRR_BSS5_Msk               (0x20UL)                  /*!< BSS5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS4_Pos               (4UL)                     /*!< BSS4 (Bit 4)                                          */
#define GPIOx_BSRR_BSS4_Msk               (0x10UL)                  /*!< BSS4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS3_Pos               (3UL)                     /*!< BSS3 (Bit 3)                                          */
#define GPIOx_BSRR_BSS3_Msk               (0x8UL)                   /*!< BSS3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS2_Pos               (2UL)                     /*!< BSS2 (Bit 2)                                          */
#define GPIOx_BSRR_BSS2_Msk               (0x4UL)                   /*!< BSS2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS1_Pos               (1UL)                     /*!< BSS1 (Bit 1)                                          */
#define GPIOx_BSRR_BSS1_Msk               (0x2UL)                   /*!< BSS1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS0_Pos               (0UL)                     /*!< BSS0 (Bit 0)                                          */
#define GPIOx_BSRR_BSS0_Msk               (0x1UL)                   /*!< BSS0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  TOG  ========================================================== */
#define GPIOx_TOG_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_TOG_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_TOG_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_TOG_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_TOG_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_TOG_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_TOG_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_TOG_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_TOG_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_TOG_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_TOG_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_TOG_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_TOG_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_TOG_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_TOG_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_TOG_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_TOG_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                           GPIOC                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  DIR  ========================================================== */
#define GPIOC_DIR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_DIR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_DIR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_DIR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_DIR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_DIR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* =======================================================  OPENDRAIN  ======================================================= */
#define GPIOC_OPENDRAIN_PIN15_Pos         (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_OPENDRAIN_PIN15_Msk         (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_OPENDRAIN_PIN14_Pos         (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_OPENDRAIN_PIN14_Msk         (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_OPENDRAIN_PIN13_Pos         (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_OPENDRAIN_PIN13_Msk         (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* =========================================================  SPEED  ========================================================= */
#define GPIOC_SPEED_PIN15_Pos             (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_SPEED_PIN15_Msk             (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_SPEED_PIN14_Pos             (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_SPEED_PIN14_Msk             (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_SPEED_PIN13_Pos             (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_SPEED_PIN13_Msk             (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  PDR  ========================================================== */
#define GPIOC_PDR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_PDR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_PDR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_PDR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_PDR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_PDR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  PUR  ========================================================== */
#define GPIOC_PUR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_PUR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_PUR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_PUR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_PUR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_PUR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* =========================================================  AFRH  ========================================================== */
#define GPIOC_AFRH_AFR15_Pos              (28UL)                    /*!< AFR15 (Bit 28)                                        */
#define GPIOC_AFRH_AFR15_Msk              (0xf0000000UL)            /*!< AFR15 (Bitfield-Mask: 0x0f)                           */
#define GPIOC_AFRH_AFR14_Pos              (24UL)                    /*!< AFR14 (Bit 24)                                        */
#define GPIOC_AFRH_AFR14_Msk              (0xf000000UL)             /*!< AFR14 (Bitfield-Mask: 0x0f)                           */
#define GPIOC_AFRH_AFR13_Pos              (20UL)                    /*!< AFR13 (Bit 20)                                        */
#define GPIOC_AFRH_AFR13_Msk              (0xf00000UL)              /*!< AFR13 (Bitfield-Mask: 0x0f)                           */
/* ========================================================  ANALOG  ========================================================= */
#define GPIOC_ANALOG_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_ANALOG_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_ANALOG_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_ANALOG_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_ANALOG_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_ANALOG_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ========================================================  DRIVER  ========================================================= */
#define GPIOC_DRIVER_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_DRIVER_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_DRIVER_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_DRIVER_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_DRIVER_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_DRIVER_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ========================================================  RISEIE  ========================================================= */
#define GPIOC_RISEIE_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_RISEIE_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_RISEIE_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_RISEIE_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_RISEIE_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_RISEIE_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ========================================================  FALLIE  ========================================================= */
#define GPIOC_FALLIE_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_FALLIE_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_FALLIE_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_FALLIE_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_FALLIE_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_FALLIE_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ========================================================  HIGHIE  ========================================================= */
#define GPIOC_HIGHIE_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_HIGHIE_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_HIGHIE_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_HIGHIE_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_HIGHIE_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_HIGHIE_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* =========================================================  LOWIE  ========================================================= */
#define GPIOC_LOWIE_PIN15_Pos             (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_LOWIE_PIN15_Msk             (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_LOWIE_PIN14_Pos             (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_LOWIE_PIN14_Msk             (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_LOWIE_PIN13_Pos             (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_LOWIE_PIN13_Msk             (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ISR  ========================================================== */
#define GPIOC_ISR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_ISR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_ISR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_ISR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_ISR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_ISR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ICR  ========================================================== */
#define GPIOC_ICR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_ICR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_ICR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_ICR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_ICR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_ICR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* =========================================================  LOCK  ========================================================== */
#define GPIOC_LOCK_KEY_Pos                (16UL)                    /*!< KEY (Bit 16)                                          */
#define GPIOC_LOCK_KEY_Msk                (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define GPIOC_LOCK_PIN15_Pos              (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_LOCK_PIN15_Msk              (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_LOCK_PIN14_Pos              (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_LOCK_PIN14_Msk              (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_LOCK_PIN13_Pos              (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_LOCK_PIN13_Msk              (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ========================================================  FILTER  ========================================================= */
#define GPIOC_FILTER_FLTCLK_Pos           (16UL)                    /*!< FLTCLK (Bit 16)                                       */
#define GPIOC_FILTER_FLTCLK_Msk           (0x70000UL)               /*!< FLTCLK (Bitfield-Mask: 0x07)                          */
#define GPIOC_FILTER_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_FILTER_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_FILTER_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_FILTER_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_FILTER_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_FILTER_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  IDR  ========================================================== */
#define GPIOC_IDR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_IDR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_IDR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_IDR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_IDR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_IDR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ODR  ========================================================== */
#define GPIOC_ODR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_ODR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_ODR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_ODR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_ODR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_ODR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
/* ======================================================  ODRLOWBYTE  ======================================================= */
#define GPIOC_ODRLOWBYTE_LOWBYTE_Pos      (0UL)                     /*!< LOWBYTE (Bit 0)                                       */
#define GPIOC_ODRLOWBYTE_LOWBYTE_Msk      (0xffUL)                  /*!< LOWBYTE (Bitfield-Mask: 0xff)                         */
/* ======================================================  ODRHIGHBYTE  ====================================================== */
#define GPIOC_ODRHIGHBYTE_HIGHBYTE_Pos    (0UL)                     /*!< HIGHBYTE (Bit 0)                                      */
#define GPIOC_ODRHIGHBYTE_HIGHBYTE_Msk    (0xffUL)                  /*!< HIGHBYTE (Bitfield-Mask: 0xff)                        */
/* ==========================================================  BRR  ========================================================== */
#define GPIOC_BRR_BRR15_Pos               (15UL)                    /*!< BRR15 (Bit 15)                                        */
#define GPIOC_BRR_BRR15_Msk               (0x8000UL)                /*!< BRR15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_BRR_BRR14_Pos               (14UL)                    /*!< BRR14 (Bit 14)                                        */
#define GPIOC_BRR_BRR14_Msk               (0x4000UL)                /*!< BRR14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_BRR_BRR13_Pos               (13UL)                    /*!< BRR13 (Bit 13)                                        */
#define GPIOC_BRR_BRR13_Msk               (0x2000UL)                /*!< BRR13 (Bitfield-Mask: 0x01)                           */
/* =========================================================  BSRR  ========================================================== */
#define GPIOC_BSRR_BRR15_Pos              (31UL)                    /*!< BRR15 (Bit 31)                                        */
#define GPIOC_BSRR_BRR15_Msk              (0x80000000UL)            /*!< BRR15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_BSRR_BRR14_Pos              (30UL)                    /*!< BRR14 (Bit 30)                                        */
#define GPIOC_BSRR_BRR14_Msk              (0x40000000UL)            /*!< BRR14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_BSRR_BRR13_Pos              (29UL)                    /*!< BRR13 (Bit 29)                                        */
#define GPIOC_BSRR_BRR13_Msk              (0x20000000UL)            /*!< BRR13 (Bitfield-Mask: 0x01)                           */
#define GPIOC_BSRR_BSS15_Pos              (15UL)                    /*!< BSS15 (Bit 15)                                        */
#define GPIOC_BSRR_BSS15_Msk              (0x8000UL)                /*!< BSS15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_BSRR_BSS14_Pos              (14UL)                    /*!< BSS14 (Bit 14)                                        */
#define GPIOC_BSRR_BSS14_Msk              (0x4000UL)                /*!< BSS14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_BSRR_BSS13_Pos              (13UL)                    /*!< BSS13 (Bit 13)                                        */
#define GPIOC_BSRR_BSS13_Msk              (0x2000UL)                /*!< BSS13 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  TOG  ========================================================== */
#define GPIOC_TOG_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOC_TOG_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOC_TOG_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOC_TOG_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOC_TOG_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOC_TOG_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                           GPIOF                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  DIR  ========================================================== */
#define GPIOF_DIR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_DIR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_DIR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_DIR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_DIR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_DIR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_DIR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_DIR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_DIR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_DIR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =======================================================  OPENDRAIN  ======================================================= */
#define GPIOF_OPENDRAIN_PIN7_Pos          (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_OPENDRAIN_PIN7_Msk          (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_OPENDRAIN_PIN6_Pos          (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_OPENDRAIN_PIN6_Msk          (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_OPENDRAIN_PIN3_Pos          (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_OPENDRAIN_PIN3_Msk          (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_OPENDRAIN_PIN1_Pos          (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_OPENDRAIN_PIN1_Msk          (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_OPENDRAIN_PIN0_Pos          (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_OPENDRAIN_PIN0_Msk          (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  SPEED  ========================================================= */
#define GPIOF_SPEED_PIN7_Pos              (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_SPEED_PIN7_Msk              (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_SPEED_PIN6_Pos              (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_SPEED_PIN6_Msk              (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_SPEED_PIN3_Pos              (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_SPEED_PIN3_Msk              (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_SPEED_PIN1_Pos              (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_SPEED_PIN1_Msk              (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_SPEED_PIN0_Pos              (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_SPEED_PIN0_Msk              (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  PDR  ========================================================== */
#define GPIOF_PDR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_PDR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_PDR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_PDR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_PDR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_PDR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_PDR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_PDR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_PDR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_PDR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  PUR  ========================================================== */
#define GPIOF_PUR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_PUR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_PUR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_PUR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_PUR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_PUR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_PUR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_PUR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_PUR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_PUR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  AFRL  ========================================================== */
#define GPIOF_AFRL_AFR7_Pos               (28UL)                    /*!< AFR7 (Bit 28)                                         */
#define GPIOF_AFRL_AFR7_Msk               (0xf0000000UL)            /*!< AFR7 (Bitfield-Mask: 0x0f)                            */
#define GPIOF_AFRL_AFR6_Pos               (24UL)                    /*!< AFR6 (Bit 24)                                         */
#define GPIOF_AFRL_AFR6_Msk               (0xf000000UL)             /*!< AFR6 (Bitfield-Mask: 0x0f)                            */
#define GPIOF_AFRL_AFR3_Pos               (12UL)                    /*!< AFR3 (Bit 12)                                         */
#define GPIOF_AFRL_AFR3_Msk               (0xf000UL)                /*!< AFR3 (Bitfield-Mask: 0x0f)                            */
#define GPIOF_AFRL_AFR1_Pos               (4UL)                     /*!< AFR1 (Bit 4)                                          */
#define GPIOF_AFRL_AFR1_Msk               (0xf0UL)                  /*!< AFR1 (Bitfield-Mask: 0x0f)                            */
#define GPIOF_AFRL_AFR0_Pos               (0UL)                     /*!< AFR0 (Bit 0)                                          */
#define GPIOF_AFRL_AFR0_Msk               (0xfUL)                   /*!< AFR0 (Bitfield-Mask: 0x0f)                            */
/* ========================================================  ANALOG  ========================================================= */
#define GPIOF_ANALOG_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_ANALOG_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ANALOG_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_ANALOG_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ANALOG_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_ANALOG_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ANALOG_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_ANALOG_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ANALOG_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_ANALOG_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  DRIVER  ========================================================= */
#define GPIOF_DRIVER_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_DRIVER_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_DRIVER_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_DRIVER_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_DRIVER_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_DRIVER_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_DRIVER_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_DRIVER_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_DRIVER_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_DRIVER_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  RISEIE  ========================================================= */
#define GPIOF_RISEIE_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_RISEIE_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_RISEIE_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_RISEIE_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_RISEIE_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_RISEIE_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_RISEIE_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_RISEIE_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_RISEIE_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_RISEIE_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  FALLIE  ========================================================= */
#define GPIOF_FALLIE_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_FALLIE_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_FALLIE_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_FALLIE_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_FALLIE_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_FALLIE_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_FALLIE_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_FALLIE_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_FALLIE_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_FALLIE_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  HIGHIE  ========================================================= */
#define GPIOF_HIGHIE_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_HIGHIE_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_HIGHIE_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_HIGHIE_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_HIGHIE_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_HIGHIE_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_HIGHIE_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_HIGHIE_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_HIGHIE_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_HIGHIE_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  LOWIE  ========================================================= */
#define GPIOF_LOWIE_PIN7_Pos              (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_LOWIE_PIN7_Msk              (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_LOWIE_PIN6_Pos              (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_LOWIE_PIN6_Msk              (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_LOWIE_PIN3_Pos              (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_LOWIE_PIN3_Msk              (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_LOWIE_PIN1_Pos              (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_LOWIE_PIN1_Msk              (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_LOWIE_PIN0_Pos              (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_LOWIE_PIN0_Msk              (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ISR  ========================================================== */
#define GPIOF_ISR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_ISR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ISR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_ISR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ISR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_ISR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ISR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_ISR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ISR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_ISR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ICR  ========================================================== */
#define GPIOF_ICR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_ICR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ICR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_ICR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ICR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_ICR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ICR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_ICR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ICR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_ICR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  LOCK  ========================================================== */
#define GPIOF_LOCK_KEY_Pos                (16UL)                    /*!< KEY (Bit 16)                                          */
#define GPIOF_LOCK_KEY_Msk                (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define GPIOF_LOCK_PIN7_Pos               (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_LOCK_PIN7_Msk               (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_LOCK_PIN6_Pos               (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_LOCK_PIN6_Msk               (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_LOCK_PIN3_Pos               (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_LOCK_PIN3_Msk               (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_LOCK_PIN1_Pos               (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_LOCK_PIN1_Msk               (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_LOCK_PIN0_Pos               (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_LOCK_PIN0_Msk               (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  FILTER  ========================================================= */
#define GPIOF_FILTER_FLTCLK_Pos           (16UL)                    /*!< FLTCLK (Bit 16)                                       */
#define GPIOF_FILTER_FLTCLK_Msk           (0x70000UL)               /*!< FLTCLK (Bitfield-Mask: 0x07)                          */
#define GPIOF_FILTER_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_FILTER_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_FILTER_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_FILTER_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_FILTER_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_FILTER_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_FILTER_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_FILTER_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_FILTER_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_FILTER_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  IDR  ========================================================== */
#define GPIOF_IDR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_IDR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_IDR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_IDR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_IDR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_IDR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_IDR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_IDR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_IDR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_IDR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ODR  ========================================================== */
#define GPIOF_ODR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_ODR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ODR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_ODR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ODR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_ODR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ODR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_ODR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_ODR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_ODR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ======================================================  ODRLOWBYTE  ======================================================= */
#define GPIOF_ODRLOWBYTE_LOWBYTE_Pos      (0UL)                     /*!< LOWBYTE (Bit 0)                                       */
#define GPIOF_ODRLOWBYTE_LOWBYTE_Msk      (0xffUL)                  /*!< LOWBYTE (Bitfield-Mask: 0xff)                         */
/* ==========================================================  BRR  ========================================================== */
#define GPIOF_BRR_BRR7_Pos                (7UL)                     /*!< BRR7 (Bit 7)                                          */
#define GPIOF_BRR_BRR7_Msk                (0x80UL)                  /*!< BRR7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_BRR_BRR6_Pos                (6UL)                     /*!< BRR6 (Bit 6)                                          */
#define GPIOF_BRR_BRR6_Msk                (0x40UL)                  /*!< BRR6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_BRR_BRR3_Pos                (3UL)                     /*!< BRR3 (Bit 3)                                          */
#define GPIOF_BRR_BRR3_Msk                (0x8UL)                   /*!< BRR3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_BRR_BRR1_Pos                (1UL)                     /*!< BRR1 (Bit 1)                                          */
#define GPIOF_BRR_BRR1_Msk                (0x2UL)                   /*!< BRR1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_BRR_BRR0_Pos                (0UL)                     /*!< BRR0 (Bit 0)                                          */
#define GPIOF_BRR_BRR0_Msk                (0x1UL)                   /*!< BRR0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  BSRR  ========================================================== */
#define GPIOF_BSRR_BSS7_Pos               (7UL)                     /*!< BSS7 (Bit 7)                                          */
#define GPIOF_BSRR_BSS7_Msk               (0x80UL)                  /*!< BSS7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_BSRR_BSS6_Pos               (6UL)                     /*!< BSS6 (Bit 6)                                          */
#define GPIOF_BSRR_BSS6_Msk               (0x40UL)                  /*!< BSS6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_BSRR_BSS3_Pos               (3UL)                     /*!< BSS3 (Bit 3)                                          */
#define GPIOF_BSRR_BSS3_Msk               (0x8UL)                   /*!< BSS3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_BSRR_BSS1_Pos               (1UL)                     /*!< BSS1 (Bit 1)                                          */
#define GPIOF_BSRR_BSS1_Msk               (0x2UL)                   /*!< BSS1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_BSRR_BSS0_Pos               (0UL)                     /*!< BSS0 (Bit 0)                                          */
#define GPIOF_BSRR_BSS0_Msk               (0x1UL)                   /*!< BSS0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  TOG  ========================================================== */
#define GPIOF_TOG_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOF_TOG_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOF_TOG_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOF_TOG_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOF_TOG_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOF_TOG_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOF_TOG_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOF_TOG_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOF_TOG_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOF_TOG_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                           GTIM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ARR  ========================================================== */
#define GTIMx_ARR_ARR_Pos                 (0UL)                     /*!< ARR (Bit 0)                                           */
#define GTIMx_ARR_ARR_Msk                 (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CNT  ========================================================== */
#define GTIMx_CNT_CNT_Pos                 (0UL)                     /*!< CNT (Bit 0)                                           */
#define GTIMx_CNT_CNT_Msk                 (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CMMR  ========================================================== */
#define GTIMx_CMMR_CC4M_Pos               (12UL)                    /*!< CC4M (Bit 12)                                         */
#define GTIMx_CMMR_CC4M_Msk               (0xf000UL)                /*!< CC4M (Bitfield-Mask: 0x0f)                            */
#define GTIMx_CMMR_CC3M_Pos               (8UL)                     /*!< CC3M (Bit 8)                                          */
#define GTIMx_CMMR_CC3M_Msk               (0xf00UL)                 /*!< CC3M (Bitfield-Mask: 0x0f)                            */
#define GTIMx_CMMR_CC2M_Pos               (4UL)                     /*!< CC2M (Bit 4)                                          */
#define GTIMx_CMMR_CC2M_Msk               (0xf0UL)                  /*!< CC2M (Bitfield-Mask: 0x0f)                            */
#define GTIMx_CMMR_CC1M_Pos               (0UL)                     /*!< CC1M (Bit 0)                                          */
#define GTIMx_CMMR_CC1M_Msk               (0xfUL)                   /*!< CC1M (Bitfield-Mask: 0x0f)                            */
/* ==========================================================  ETR  ========================================================== */
#define GTIMx_ETR_ETRFLT_Pos              (4UL)                     /*!< ETRFLT (Bit 4)                                        */
#define GTIMx_ETR_ETRFLT_Msk              (0x70UL)                  /*!< ETRFLT (Bitfield-Mask: 0x07)                          */
/* ==========================================================  CR0  ========================================================== */
#define GTIMx_CR0_ENCRELOAD_Pos           (19UL)                    /*!< ENCRELOAD (Bit 19)                                    */
#define GTIMx_CR0_ENCRELOAD_Msk           (0x180000UL)              /*!< ENCRELOAD (Bitfield-Mask: 0x03)                       */
#define GTIMx_CR0_ENCRESET_Pos            (17UL)                    /*!< ENCRESET (Bit 17)                                     */
#define GTIMx_CR0_ENCRESET_Msk            (0x60000UL)               /*!< ENCRESET (Bitfield-Mask: 0x03)                        */
#define GTIMx_CR0_ENCMODE_Pos             (15UL)                    /*!< ENCMODE (Bit 15)                                      */
#define GTIMx_CR0_ENCMODE_Msk             (0x18000UL)               /*!< ENCMODE (Bitfield-Mask: 0x03)                         */
#define GTIMx_CR0_PRSSTATUS_Pos           (11UL)                    /*!< PRSSTATUS (Bit 11)                                    */
#define GTIMx_CR0_PRSSTATUS_Msk           (0x7800UL)                /*!< PRSSTATUS (Bitfield-Mask: 0x0f)                       */
#define GTIMx_CR0_PRS_Pos                 (7UL)                     /*!< PRS (Bit 7)                                           */
#define GTIMx_CR0_PRS_Msk                 (0x780UL)                 /*!< PRS (Bitfield-Mask: 0x0f)                             */
#define GTIMx_CR0_TOGEN_Pos               (6UL)                     /*!< TOGEN (Bit 6)                                         */
#define GTIMx_CR0_TOGEN_Msk               (0x40UL)                  /*!< TOGEN (Bitfield-Mask: 0x01)                           */
#define GTIMx_CR0_ONESHOT_Pos             (5UL)                     /*!< ONESHOT (Bit 5)                                       */
#define GTIMx_CR0_ONESHOT_Msk             (0x20UL)                  /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
#define GTIMx_CR0_POL_Pos                 (4UL)                     /*!< POL (Bit 4)                                           */
#define GTIMx_CR0_POL_Msk                 (0x10UL)                  /*!< POL (Bitfield-Mask: 0x01)                             */
#define GTIMx_CR0_TRS_Pos                 (3UL)                     /*!< TRS (Bit 3)                                           */
#define GTIMx_CR0_TRS_Msk                 (0x8UL)                   /*!< TRS (Bitfield-Mask: 0x01)                             */
#define GTIMx_CR0_MODE_Pos                (1UL)                     /*!< MODE (Bit 1)                                          */
#define GTIMx_CR0_MODE_Msk                (0x6UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
#define GTIMx_CR0_EN_Pos                  (0UL)                     /*!< EN (Bit 0)                                            */
#define GTIMx_CR0_EN_Msk                  (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  IER  ========================================================== */
#define GTIMx_IER_DIRCHANGE_Pos           (9UL)                     /*!< DIRCHANGE (Bit 9)                                     */
#define GTIMx_IER_DIRCHANGE_Msk           (0x200UL)                 /*!< DIRCHANGE (Bitfield-Mask: 0x01)                       */
#define GTIMx_IER_CC4_Pos                 (6UL)                     /*!< CC4 (Bit 6)                                           */
#define GTIMx_IER_CC4_Msk                 (0x40UL)                  /*!< CC4 (Bitfield-Mask: 0x01)                             */
#define GTIMx_IER_CC3_Pos                 (5UL)                     /*!< CC3 (Bit 5)                                           */
#define GTIMx_IER_CC3_Msk                 (0x20UL)                  /*!< CC3 (Bitfield-Mask: 0x01)                             */
#define GTIMx_IER_CC2_Pos                 (4UL)                     /*!< CC2 (Bit 4)                                           */
#define GTIMx_IER_CC2_Msk                 (0x10UL)                  /*!< CC2 (Bitfield-Mask: 0x01)                             */
#define GTIMx_IER_CC1_Pos                 (3UL)                     /*!< CC1 (Bit 3)                                           */
#define GTIMx_IER_CC1_Msk                 (0x8UL)                   /*!< CC1 (Bitfield-Mask: 0x01)                             */
#define GTIMx_IER_UD_Pos                  (2UL)                     /*!< UD (Bit 2)                                            */
#define GTIMx_IER_UD_Msk                  (0x4UL)                   /*!< UD (Bitfield-Mask: 0x01)                              */
#define GTIMx_IER_TI_Pos                  (1UL)                     /*!< TI (Bit 1)                                            */
#define GTIMx_IER_TI_Msk                  (0x2UL)                   /*!< TI (Bitfield-Mask: 0x01)                              */
#define GTIMx_IER_OV_Pos                  (0UL)                     /*!< OV (Bit 0)                                            */
#define GTIMx_IER_OV_Msk                  (0x1UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ISR  ========================================================== */
#define GTIMx_ISR_DIR_Pos                 (10UL)                    /*!< DIR (Bit 10)                                          */
#define GTIMx_ISR_DIR_Msk                 (0x400UL)                 /*!< DIR (Bitfield-Mask: 0x01)                             */
#define GTIMx_ISR_DIRCHANGE_Pos           (9UL)                     /*!< DIRCHANGE (Bit 9)                                     */
#define GTIMx_ISR_DIRCHANGE_Msk           (0x200UL)                 /*!< DIRCHANGE (Bitfield-Mask: 0x01)                       */
#define GTIMx_ISR_CC4_Pos                 (6UL)                     /*!< CC4 (Bit 6)                                           */
#define GTIMx_ISR_CC4_Msk                 (0x40UL)                  /*!< CC4 (Bitfield-Mask: 0x01)                             */
#define GTIMx_ISR_CC3_Pos                 (5UL)                     /*!< CC3 (Bit 5)                                           */
#define GTIMx_ISR_CC3_Msk                 (0x20UL)                  /*!< CC3 (Bitfield-Mask: 0x01)                             */
#define GTIMx_ISR_CC2_Pos                 (4UL)                     /*!< CC2 (Bit 4)                                           */
#define GTIMx_ISR_CC2_Msk                 (0x10UL)                  /*!< CC2 (Bitfield-Mask: 0x01)                             */
#define GTIMx_ISR_CC1_Pos                 (3UL)                     /*!< CC1 (Bit 3)                                           */
#define GTIMx_ISR_CC1_Msk                 (0x8UL)                   /*!< CC1 (Bitfield-Mask: 0x01)                             */
#define GTIMx_ISR_UD_Pos                  (2UL)                     /*!< UD (Bit 2)                                            */
#define GTIMx_ISR_UD_Msk                  (0x4UL)                   /*!< UD (Bitfield-Mask: 0x01)                              */
#define GTIMx_ISR_TI_Pos                  (1UL)                     /*!< TI (Bit 1)                                            */
#define GTIMx_ISR_TI_Msk                  (0x2UL)                   /*!< TI (Bitfield-Mask: 0x01)                              */
#define GTIMx_ISR_OV_Pos                  (0UL)                     /*!< OV (Bit 0)                                            */
#define GTIMx_ISR_OV_Msk                  (0x1UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ICR  ========================================================== */
#define GTIMx_ICR_DIRCHANGE_Pos           (9UL)                     /*!< DIRCHANGE (Bit 9)                                     */
#define GTIMx_ICR_DIRCHANGE_Msk           (0x200UL)                 /*!< DIRCHANGE (Bitfield-Mask: 0x01)                       */
#define GTIMx_ICR_CC4_Pos                 (6UL)                     /*!< CC4 (Bit 6)                                           */
#define GTIMx_ICR_CC4_Msk                 (0x40UL)                  /*!< CC4 (Bitfield-Mask: 0x01)                             */
#define GTIMx_ICR_CC3_Pos                 (5UL)                     /*!< CC3 (Bit 5)                                           */
#define GTIMx_ICR_CC3_Msk                 (0x20UL)                  /*!< CC3 (Bitfield-Mask: 0x01)                             */
#define GTIMx_ICR_CC2_Pos                 (4UL)                     /*!< CC2 (Bit 4)                                           */
#define GTIMx_ICR_CC2_Msk                 (0x10UL)                  /*!< CC2 (Bitfield-Mask: 0x01)                             */
#define GTIMx_ICR_CC1_Pos                 (3UL)                     /*!< CC1 (Bit 3)                                           */
#define GTIMx_ICR_CC1_Msk                 (0x8UL)                   /*!< CC1 (Bitfield-Mask: 0x01)                             */
#define GTIMx_ICR_UD_Pos                  (2UL)                     /*!< UD (Bit 2)                                            */
#define GTIMx_ICR_UD_Msk                  (0x4UL)                   /*!< UD (Bitfield-Mask: 0x01)                              */
#define GTIMx_ICR_TI_Pos                  (1UL)                     /*!< TI (Bit 1)                                            */
#define GTIMx_ICR_TI_Msk                  (0x2UL)                   /*!< TI (Bitfield-Mask: 0x01)                              */
#define GTIMx_ICR_OV_Pos                  (0UL)                     /*!< OV (Bit 0)                                            */
#define GTIMx_ICR_OV_Msk                  (0x1UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
/* =========================================================  CCR1  ========================================================== */
#define GTIMx_CCR1_CCR_Pos                (0UL)                     /*!< CCR (Bit 0)                                           */
#define GTIMx_CCR1_CCR_Msk                (0xffffUL)                /*!< CCR (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CCR2  ========================================================== */
#define GTIMx_CCR2_CCR_Pos                (0UL)                     /*!< CCR (Bit 0)                                           */
#define GTIMx_CCR2_CCR_Msk                (0xffffUL)                /*!< CCR (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CCR3  ========================================================== */
#define GTIMx_CCR3_CCR_Pos                (0UL)                     /*!< CCR (Bit 0)                                           */
#define GTIMx_CCR3_CCR_Msk                (0xffffUL)                /*!< CCR (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CCR4  ========================================================== */
#define GTIMx_CCR4_CCR_Pos                (0UL)                     /*!< CCR (Bit 0)                                           */
#define GTIMx_CCR4_CCR_Msk                (0xffffUL)                /*!< CCR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CR1  ========================================================== */
#define GTIMx_CR1_CH4POL_Pos              (15UL)                    /*!< CH4POL (Bit 15)                                       */
#define GTIMx_CR1_CH4POL_Msk              (0x8000UL)                /*!< CH4POL (Bitfield-Mask: 0x01)                          */
#define GTIMx_CR1_CH4FLT_Pos              (12UL)                    /*!< CH4FLT (Bit 12)                                       */
#define GTIMx_CR1_CH4FLT_Msk              (0x7000UL)                /*!< CH4FLT (Bitfield-Mask: 0x07)                          */
#define GTIMx_CR1_CH3POL_Pos              (11UL)                    /*!< CH3POL (Bit 11)                                       */
#define GTIMx_CR1_CH3POL_Msk              (0x800UL)                 /*!< CH3POL (Bitfield-Mask: 0x01)                          */
#define GTIMx_CR1_CH3FLT_Pos              (8UL)                     /*!< CH3FLT (Bit 8)                                        */
#define GTIMx_CR1_CH3FLT_Msk              (0x700UL)                 /*!< CH3FLT (Bitfield-Mask: 0x07)                          */
#define GTIMx_CR1_CH2POL_Pos              (7UL)                     /*!< CH2POL (Bit 7)                                        */
#define GTIMx_CR1_CH2POL_Msk              (0x80UL)                  /*!< CH2POL (Bitfield-Mask: 0x01)                          */
#define GTIMx_CR1_CH2FLT_Pos              (4UL)                     /*!< CH2FLT (Bit 4)                                        */
#define GTIMx_CR1_CH2FLT_Msk              (0x70UL)                  /*!< CH2FLT (Bitfield-Mask: 0x07)                          */
#define GTIMx_CR1_CH1POL_Pos              (3UL)                     /*!< CH1POL (Bit 3)                                        */
#define GTIMx_CR1_CH1POL_Msk              (0x8UL)                   /*!< CH1POL (Bitfield-Mask: 0x01)                          */
#define GTIMx_CR1_CH1FLT_Pos              (0UL)                     /*!< CH1FLT (Bit 0)                                        */
#define GTIMx_CR1_CH1FLT_Msk              (0x7UL)                   /*!< CH1FLT (Bitfield-Mask: 0x07)                          */
/* ==========================================================  DMA  ========================================================== */
#define GTIMx_DMA_CC4_Pos                 (5UL)                     /*!< CC4 (Bit 5)                                           */
#define GTIMx_DMA_CC4_Msk                 (0x20UL)                  /*!< CC4 (Bitfield-Mask: 0x01)                             */
#define GTIMx_DMA_CC3_Pos                 (4UL)                     /*!< CC3 (Bit 4)                                           */
#define GTIMx_DMA_CC3_Msk                 (0x10UL)                  /*!< CC3 (Bitfield-Mask: 0x01)                             */
#define GTIMx_DMA_CC2_Pos                 (3UL)                     /*!< CC2 (Bit 3)                                           */
#define GTIMx_DMA_CC2_Msk                 (0x8UL)                   /*!< CC2 (Bitfield-Mask: 0x01)                             */
#define GTIMx_DMA_CC1_Pos                 (2UL)                     /*!< CC1 (Bit 2)                                           */
#define GTIMx_DMA_CC1_Msk                 (0x4UL)                   /*!< CC1 (Bitfield-Mask: 0x01)                             */
#define GTIMx_DMA_TRS_Pos                 (1UL)                     /*!< TRS (Bit 1)                                           */
#define GTIMx_DMA_TRS_Msk                 (0x2UL)                   /*!< TRS (Bitfield-Mask: 0x01)                             */
#define GTIMx_DMA_OV_Pos                  (0UL)                     /*!< OV (Bit 0)                                            */
#define GTIMx_DMA_OV_Msk                  (0x1UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */


/* =========================================================================================================================== */
/* ================                                            I2C                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  BRREN  ========================================================= */
#define I2Cx_BRREN_EN_Pos                 (0UL)                     /*!< EN (Bit 0)                                            */
#define I2Cx_BRREN_EN_Msk                 (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  BRR  ========================================================== */
#define I2Cx_BRR_BRR_Pos                  (0UL)                     /*!< BRR (Bit 0)                                           */
#define I2Cx_BRR_BRR_Msk                  (0xffUL)                  /*!< BRR (Bitfield-Mask: 0xff)                             */
/* ==========================================================  CR  =========================================================== */
#define I2Cx_CR_EN_Pos                    (6UL)                     /*!< EN (Bit 6)                                            */
#define I2Cx_CR_EN_Msk                    (0x40UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define I2Cx_CR_STA_Pos                   (5UL)                     /*!< STA (Bit 5)                                           */
#define I2Cx_CR_STA_Msk                   (0x20UL)                  /*!< STA (Bitfield-Mask: 0x01)                             */
#define I2Cx_CR_STO_Pos                   (4UL)                     /*!< STO (Bit 4)                                           */
#define I2Cx_CR_STO_Msk                   (0x10UL)                  /*!< STO (Bitfield-Mask: 0x01)                             */
#define I2Cx_CR_SI_Pos                    (3UL)                     /*!< SI (Bit 3)                                            */
#define I2Cx_CR_SI_Msk                    (0x8UL)                   /*!< SI (Bitfield-Mask: 0x01)                              */
#define I2Cx_CR_AA_Pos                    (2UL)                     /*!< AA (Bit 2)                                            */
#define I2Cx_CR_AA_Msk                    (0x4UL)                   /*!< AA (Bitfield-Mask: 0x01)                              */
#define I2Cx_CR_FLT_Pos                   (0UL)                     /*!< FLT (Bit 0)                                           */
#define I2Cx_CR_FLT_Msk                   (0x1UL)                   /*!< FLT (Bitfield-Mask: 0x01)                             */
/* ==========================================================  DR  =========================================================== */
#define I2Cx_DR_DR_Pos                    (0UL)                     /*!< DR (Bit 0)                                            */
#define I2Cx_DR_DR_Msk                    (0xffUL)                  /*!< DR (Bitfield-Mask: 0xff)                              */
/* =========================================================  ADDR0  ========================================================= */
#define I2Cx_ADDR0_ADDR0_Pos              (1UL)                     /*!< ADDR0 (Bit 1)                                         */
#define I2Cx_ADDR0_ADDR0_Msk              (0xfeUL)                  /*!< ADDR0 (Bitfield-Mask: 0x7f)                           */
#define I2Cx_ADDR0_GC_Pos                 (0UL)                     /*!< GC (Bit 0)                                            */
#define I2Cx_ADDR0_GC_Msk                 (0x1UL)                   /*!< GC (Bitfield-Mask: 0x01)                              */
/* =========================================================  STAT  ========================================================== */
#define I2Cx_STAT_STAT_Pos                (0UL)                     /*!< STAT (Bit 0)                                          */
#define I2Cx_STAT_STAT_Msk                (0xffUL)                  /*!< STAT (Bitfield-Mask: 0xff)                            */
/* =========================================================  ADDR1  ========================================================= */
#define I2Cx_ADDR1_ADDR1_Pos              (1UL)                     /*!< ADDR1 (Bit 1)                                         */
#define I2Cx_ADDR1_ADDR1_Msk              (0xfeUL)                  /*!< ADDR1 (Bitfield-Mask: 0x7f)                           */
/* =========================================================  ADDR2  ========================================================= */
#define I2Cx_ADDR2_ADDR2_Pos              (1UL)                     /*!< ADDR2 (Bit 1)                                         */
#define I2Cx_ADDR2_ADDR2_Msk              (0xfeUL)                  /*!< ADDR2 (Bitfield-Mask: 0x7f)                           */
/* =========================================================  MATCH  ========================================================= */
#define I2Cx_MATCH_ADDR2_Pos              (2UL)                     /*!< ADDR2 (Bit 2)                                         */
#define I2Cx_MATCH_ADDR2_Msk              (0x4UL)                   /*!< ADDR2 (Bitfield-Mask: 0x01)                           */
#define I2Cx_MATCH_ADDR1_Pos              (1UL)                     /*!< ADDR1 (Bit 1)                                         */
#define I2Cx_MATCH_ADDR1_Msk              (0x2UL)                   /*!< ADDR1 (Bitfield-Mask: 0x01)                           */
#define I2Cx_MATCH_ADDR0_Pos              (0UL)                     /*!< ADDR0 (Bit 0)                                         */
#define I2Cx_MATCH_ADDR0_Msk              (0x1UL)                   /*!< ADDR0 (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                           IWDT                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  KR  =========================================================== */
#define IWDT_KR_KR_Pos                    (0UL)                     /*!< KR (Bit 0)                                            */
#define IWDT_KR_KR_Msk                    (0xffffUL)                /*!< KR (Bitfield-Mask: 0xffff)                            */
/* ==========================================================  CR  =========================================================== */
#define IWDT_CR_PAUSE_Pos                 (5UL)                     /*!< PAUSE (Bit 5)                                         */
#define IWDT_CR_PAUSE_Msk                 (0x20UL)                  /*!< PAUSE (Bitfield-Mask: 0x01)                           */
#define IWDT_CR_IE_Pos                    (4UL)                     /*!< IE (Bit 4)                                            */
#define IWDT_CR_IE_Msk                    (0x10UL)                  /*!< IE (Bitfield-Mask: 0x01)                              */
#define IWDT_CR_ACTION_Pos                (3UL)                     /*!< ACTION (Bit 3)                                        */
#define IWDT_CR_ACTION_Msk                (0x8UL)                   /*!< ACTION (Bitfield-Mask: 0x01)                          */
#define IWDT_CR_PRS_Pos                   (0UL)                     /*!< PRS (Bit 0)                                           */
#define IWDT_CR_PRS_Msk                   (0x7UL)                   /*!< PRS (Bitfield-Mask: 0x07)                             */
/* ==========================================================  ARR  ========================================================== */
#define IWDT_ARR_ARR_Pos                  (0UL)                     /*!< ARR (Bit 0)                                           */
#define IWDT_ARR_ARR_Msk                  (0xfffUL)                 /*!< ARR (Bitfield-Mask: 0xfff)                            */
/* ==========================================================  SR  =========================================================== */
#define IWDT_SR_RELOAD_Pos                (5UL)                     /*!< RELOAD (Bit 5)                                        */
#define IWDT_SR_RELOAD_Msk                (0x20UL)                  /*!< RELOAD (Bitfield-Mask: 0x01)                          */
#define IWDT_SR_RUN_Pos                   (4UL)                     /*!< RUN (Bit 4)                                           */
#define IWDT_SR_RUN_Msk                   (0x10UL)                  /*!< RUN (Bitfield-Mask: 0x01)                             */
#define IWDT_SR_OV_Pos                    (3UL)                     /*!< OV (Bit 3)                                            */
#define IWDT_SR_OV_Msk                    (0x8UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
#define IWDT_SR_WINRF_Pos                 (2UL)                     /*!< WINRF (Bit 2)                                         */
#define IWDT_SR_WINRF_Msk                 (0x4UL)                   /*!< WINRF (Bitfield-Mask: 0x01)                           */
#define IWDT_SR_ARRF_Pos                  (1UL)                     /*!< ARRF (Bit 1)                                          */
#define IWDT_SR_ARRF_Msk                  (0x2UL)                   /*!< ARRF (Bitfield-Mask: 0x01)                            */
#define IWDT_SR_CRF_Pos                   (0UL)                     /*!< CRF (Bit 0)                                           */
#define IWDT_SR_CRF_Msk                   (0x1UL)                   /*!< CRF (Bitfield-Mask: 0x01)                             */
/* =========================================================  WINR  ========================================================== */
#define IWDT_WINR_WINR_Pos                (0UL)                     /*!< WINR (Bit 0)                                          */
#define IWDT_WINR_WINR_Msk                (0xfffUL)                 /*!< WINR (Bitfield-Mask: 0xfff)                           */
/* ==========================================================  CNT  ========================================================== */
#define IWDT_CNT_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define IWDT_CNT_CNT_Msk                  (0xfffUL)                 /*!< CNT (Bitfield-Mask: 0xfff)                            */


/* =========================================================================================================================== */
/* ================                                            LVD                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define LVD_CR0_IE_Pos                    (9UL)                     /*!< IE (Bit 9)                                            */
#define LVD_CR0_IE_Msk                    (0x200UL)                 /*!< IE (Bitfield-Mask: 0x01)                              */
#define LVD_CR0_VTH_Pos                   (4UL)                     /*!< VTH (Bit 4)                                           */
#define LVD_CR0_VTH_Msk                   (0xf0UL)                  /*!< VTH (Bitfield-Mask: 0x0f)                             */
#define LVD_CR0_SOURCE_Pos                (2UL)                     /*!< SOURCE (Bit 2)                                        */
#define LVD_CR0_SOURCE_Msk                (0xcUL)                   /*!< SOURCE (Bitfield-Mask: 0x03)                          */
#define LVD_CR0_ACTION_Pos                (1UL)                     /*!< ACTION (Bit 1)                                        */
#define LVD_CR0_ACTION_Msk                (0x2UL)                   /*!< ACTION (Bitfield-Mask: 0x01)                          */
#define LVD_CR0_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define LVD_CR0_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR1  ========================================================== */
#define LVD_CR1_LEVEL_Pos                 (7UL)                     /*!< LEVEL (Bit 7)                                         */
#define LVD_CR1_LEVEL_Msk                 (0x80UL)                  /*!< LEVEL (Bitfield-Mask: 0x01)                           */
#define LVD_CR1_FALL_Pos                  (6UL)                     /*!< FALL (Bit 6)                                          */
#define LVD_CR1_FALL_Msk                  (0x40UL)                  /*!< FALL (Bitfield-Mask: 0x01)                            */
#define LVD_CR1_RISE_Pos                  (5UL)                     /*!< RISE (Bit 5)                                          */
#define LVD_CR1_RISE_Msk                  (0x20UL)                  /*!< RISE (Bitfield-Mask: 0x01)                            */
#define LVD_CR1_FLTCLK_Pos                (4UL)                     /*!< FLTCLK (Bit 4)                                        */
#define LVD_CR1_FLTCLK_Msk                (0x10UL)                  /*!< FLTCLK (Bitfield-Mask: 0x01)                          */
#define LVD_CR1_FLTTIME_Pos               (1UL)                     /*!< FLTTIME (Bit 1)                                       */
#define LVD_CR1_FLTTIME_Msk               (0xeUL)                   /*!< FLTTIME (Bitfield-Mask: 0x07)                         */
#define LVD_CR1_FLTEN_Pos                 (0UL)                     /*!< FLTEN (Bit 0)                                         */
#define LVD_CR1_FLTEN_Msk                 (0x1UL)                   /*!< FLTEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR  =========================================================== */
#define LVD_SR_FLTV_Pos                   (1UL)                     /*!< FLTV (Bit 1)                                          */
#define LVD_SR_FLTV_Msk                   (0x2UL)                   /*!< FLTV (Bitfield-Mask: 0x01)                            */
#define LVD_SR_INTF_Pos                   (0UL)                     /*!< INTF (Bit 0)                                          */
#define LVD_SR_INTF_Msk                   (0x1UL)                   /*!< INTF (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                            RAM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  IER  ========================================================== */
#define RAM_IER_PARITY_Pos                (1UL)                     /*!< PARITY (Bit 1)                                        */
#define RAM_IER_PARITY_Msk                (0x2UL)                   /*!< PARITY (Bitfield-Mask: 0x01)                          */
#define RAM_IER_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define RAM_IER_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  ADDR  ========================================================== */
#define RAM_ADDR_ADDR_Pos                 (0UL)                     /*!< ADDR (Bit 0)                                          */
#define RAM_ADDR_ADDR_Msk                 (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  ISR  ========================================================== */
#define RAM_ISR_PARITY_Pos                (0UL)                     /*!< PARITY (Bit 0)                                        */
#define RAM_ISR_PARITY_Msk                (0x1UL)                   /*!< PARITY (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
#define RAM_ICR_PARITY_Pos                (0UL)                     /*!< PARITY (Bit 0)                                        */
#define RAM_ICR_PARITY_Msk                (0x1UL)                   /*!< PARITY (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  KEY  ========================================================== */
#define RTC_KEY_KEY_Pos                   (0UL)                     /*!< KEY (Bit 0)                                           */
#define RTC_KEY_KEY_Msk                   (0xffUL)                  /*!< KEY (Bitfield-Mask: 0xff)                             */
/* ==========================================================  CR0  ========================================================== */
#define RTC_CR0_START_Pos                 (7UL)                     /*!< START (Bit 7)                                         */
#define RTC_CR0_START_Msk                 (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define RTC_CR0_RTC1HZ_Pos                (5UL)                     /*!< RTC1HZ (Bit 5)                                        */
#define RTC_CR0_RTC1HZ_Msk                (0x60UL)                  /*!< RTC1HZ (Bitfield-Mask: 0x03)                          */
#define RTC_CR0_H24_Pos                   (3UL)                     /*!< H24 (Bit 3)                                           */
#define RTC_CR0_H24_Msk                   (0x8UL)                   /*!< H24 (Bitfield-Mask: 0x01)                             */
#define RTC_CR0_INTERVAL_Pos              (0UL)                     /*!< INTERVAL (Bit 0)                                      */
#define RTC_CR0_INTERVAL_Msk              (0x7UL)                   /*!< INTERVAL (Bitfield-Mask: 0x07)                        */
/* ==========================================================  CR1  ========================================================== */
#define RTC_CR1_SOURCE_Pos                (8UL)                     /*!< SOURCE (Bit 8)                                        */
#define RTC_CR1_SOURCE_Msk                (0x700UL)                 /*!< SOURCE (Bitfield-Mask: 0x07)                          */
#define RTC_CR1_WINDOW_Pos                (1UL)                     /*!< WINDOW (Bit 1)                                        */
#define RTC_CR1_WINDOW_Msk                (0x2UL)                   /*!< WINDOW (Bitfield-Mask: 0x01)                          */
#define RTC_CR1_ACCESS_Pos                (0UL)                     /*!< ACCESS (Bit 0)                                        */
#define RTC_CR1_ACCESS_Msk                (0x1UL)                   /*!< ACCESS (Bitfield-Mask: 0x01)                          */
/* ==========================================================  CR2  ========================================================== */
#define RTC_CR2_ALARMBEN_Pos              (10UL)                    /*!< ALARMBEN (Bit 10)                                     */
#define RTC_CR2_ALARMBEN_Msk              (0x400UL)                 /*!< ALARMBEN (Bitfield-Mask: 0x01)                        */
#define RTC_CR2_ALARMAEN_Pos              (9UL)                     /*!< ALARMAEN (Bit 9)                                      */
#define RTC_CR2_ALARMAEN_Msk              (0x200UL)                 /*!< ALARMAEN (Bitfield-Mask: 0x01)                        */
#define RTC_CR2_AWTEN_Pos                 (7UL)                     /*!< AWTEN (Bit 7)                                         */
#define RTC_CR2_AWTEN_Msk                 (0x80UL)                  /*!< AWTEN (Bitfield-Mask: 0x01)                           */
#define RTC_CR2_TAMPEN_Pos                (6UL)                     /*!< TAMPEN (Bit 6)                                        */
#define RTC_CR2_TAMPEN_Msk                (0x40UL)                  /*!< TAMPEN (Bitfield-Mask: 0x01)                          */
#define RTC_CR2_RTCOUT_Pos                (4UL)                     /*!< RTCOUT (Bit 4)                                        */
#define RTC_CR2_RTCOUT_Msk                (0x30UL)                  /*!< RTCOUT (Bitfield-Mask: 0x03)                          */
#define RTC_CR2_TAMPEDGE_Pos              (3UL)                     /*!< TAMPEDGE (Bit 3)                                      */
#define RTC_CR2_TAMPEDGE_Msk              (0x8UL)                   /*!< TAMPEDGE (Bitfield-Mask: 0x01)                        */
#define RTC_CR2_AWTSRC_Pos                (0UL)                     /*!< AWTSRC (Bit 0)                                        */
#define RTC_CR2_AWTSRC_Msk                (0x7UL)                   /*!< AWTSRC (Bitfield-Mask: 0x07)                          */
/* ========================================================  COMPEN  ========================================================= */
#define RTC_COMPEN_FREQ_Pos               (16UL)                    /*!< FREQ (Bit 16)                                         */
#define RTC_COMPEN_FREQ_Msk               (0xf0000UL)               /*!< FREQ (Bitfield-Mask: 0x0f)                            */
#define RTC_COMPEN_EN_Pos                 (15UL)                    /*!< EN (Bit 15)                                           */
#define RTC_COMPEN_EN_Msk                 (0x8000UL)                /*!< EN (Bitfield-Mask: 0x01)                              */
#define RTC_COMPEN_SIGN_Pos               (14UL)                    /*!< SIGN (Bit 14)                                         */
#define RTC_COMPEN_SIGN_Msk               (0x4000UL)                /*!< SIGN (Bitfield-Mask: 0x01)                            */
#define RTC_COMPEN_STEP_Pos               (12UL)                    /*!< STEP (Bit 12)                                         */
#define RTC_COMPEN_STEP_Msk               (0x3000UL)                /*!< STEP (Bitfield-Mask: 0x03)                            */
#define RTC_COMPEN_COMP_Pos               (0UL)                     /*!< COMP (Bit 0)                                          */
#define RTC_COMPEN_COMP_Msk               (0xfffUL)                 /*!< COMP (Bitfield-Mask: 0xfff)                           */
/* =========================================================  DATE  ========================================================== */
#define RTC_DATE_WEEK_Pos                 (24UL)                    /*!< WEEK (Bit 24)                                         */
#define RTC_DATE_WEEK_Msk                 (0x7000000UL)             /*!< WEEK (Bitfield-Mask: 0x07)                            */
#define RTC_DATE_YEAR_Pos                 (16UL)                    /*!< YEAR (Bit 16)                                         */
#define RTC_DATE_YEAR_Msk                 (0xff0000UL)              /*!< YEAR (Bitfield-Mask: 0xff)                            */
#define RTC_DATE_MONTH_Pos                (8UL)                     /*!< MONTH (Bit 8)                                         */
#define RTC_DATE_MONTH_Msk                (0xff00UL)                /*!< MONTH (Bitfield-Mask: 0xff)                           */
#define RTC_DATE_DAY_Pos                  (0UL)                     /*!< DAY (Bit 0)                                           */
#define RTC_DATE_DAY_Msk                  (0xffUL)                  /*!< DAY (Bitfield-Mask: 0xff)                             */
/* =========================================================  TIME  ========================================================== */
#define RTC_TIME_HOUR_Pos                 (16UL)                    /*!< HOUR (Bit 16)                                         */
#define RTC_TIME_HOUR_Msk                 (0x3f0000UL)              /*!< HOUR (Bitfield-Mask: 0x3f)                            */
#define RTC_TIME_MINUTE_Pos               (8UL)                     /*!< MINUTE (Bit 8)                                        */
#define RTC_TIME_MINUTE_Msk               (0x7f00UL)                /*!< MINUTE (Bitfield-Mask: 0x7f)                          */
#define RTC_TIME_SECOND_Pos               (0UL)                     /*!< SECOND (Bit 0)                                        */
#define RTC_TIME_SECOND_Msk               (0x7fUL)                  /*!< SECOND (Bitfield-Mask: 0x7f)                          */
/* ========================================================  ALARMA  ========================================================= */
#define RTC_ALARMA_WEEK_Pos               (24UL)                    /*!< WEEK (Bit 24)                                         */
#define RTC_ALARMA_WEEK_Msk               (0x7f000000UL)            /*!< WEEK (Bitfield-Mask: 0x7f)                            */
#define RTC_ALARMA_HOURMASK_Pos           (23UL)                    /*!< HOURMASK (Bit 23)                                     */
#define RTC_ALARMA_HOURMASK_Msk           (0x800000UL)              /*!< HOURMASK (Bitfield-Mask: 0x01)                        */
#define RTC_ALARMA_HOUR_Pos               (16UL)                    /*!< HOUR (Bit 16)                                         */
#define RTC_ALARMA_HOUR_Msk               (0x3f0000UL)              /*!< HOUR (Bitfield-Mask: 0x3f)                            */
#define RTC_ALARMA_MINUTEMASK_Pos         (15UL)                    /*!< MINUTEMASK (Bit 15)                                   */
#define RTC_ALARMA_MINUTEMASK_Msk         (0x8000UL)                /*!< MINUTEMASK (Bitfield-Mask: 0x01)                      */
#define RTC_ALARMA_MINUTE_Pos             (8UL)                     /*!< MINUTE (Bit 8)                                        */
#define RTC_ALARMA_MINUTE_Msk             (0x7f00UL)                /*!< MINUTE (Bitfield-Mask: 0x7f)                          */
#define RTC_ALARMA_SECONDMASK_Pos         (7UL)                     /*!< SECONDMASK (Bit 7)                                    */
#define RTC_ALARMA_SECONDMASK_Msk         (0x80UL)                  /*!< SECONDMASK (Bitfield-Mask: 0x01)                      */
#define RTC_ALARMA_SECOND_Pos             (0UL)                     /*!< SECOND (Bit 0)                                        */
#define RTC_ALARMA_SECOND_Msk             (0x7fUL)                  /*!< SECOND (Bitfield-Mask: 0x7f)                          */
/* ========================================================  ALARMB  ========================================================= */
#define RTC_ALARMB_WEEK_Pos               (24UL)                    /*!< WEEK (Bit 24)                                         */
#define RTC_ALARMB_WEEK_Msk               (0x7f000000UL)            /*!< WEEK (Bitfield-Mask: 0x7f)                            */
#define RTC_ALARMB_HOURMASK_Pos           (23UL)                    /*!< HOURMASK (Bit 23)                                     */
#define RTC_ALARMB_HOURMASK_Msk           (0x800000UL)              /*!< HOURMASK (Bitfield-Mask: 0x01)                        */
#define RTC_ALARMB_HOUR_Pos               (16UL)                    /*!< HOUR (Bit 16)                                         */
#define RTC_ALARMB_HOUR_Msk               (0x3f0000UL)              /*!< HOUR (Bitfield-Mask: 0x3f)                            */
#define RTC_ALARMB_MINUTEMASK_Pos         (15UL)                    /*!< MINUTEMASK (Bit 15)                                   */
#define RTC_ALARMB_MINUTEMASK_Msk         (0x8000UL)                /*!< MINUTEMASK (Bitfield-Mask: 0x01)                      */
#define RTC_ALARMB_MINUTE_Pos             (8UL)                     /*!< MINUTE (Bit 8)                                        */
#define RTC_ALARMB_MINUTE_Msk             (0x7f00UL)                /*!< MINUTE (Bitfield-Mask: 0x7f)                          */
#define RTC_ALARMB_SECONDMASK_Pos         (7UL)                     /*!< SECONDMASK (Bit 7)                                    */
#define RTC_ALARMB_SECONDMASK_Msk         (0x80UL)                  /*!< SECONDMASK (Bitfield-Mask: 0x01)                      */
#define RTC_ALARMB_SECOND_Pos             (0UL)                     /*!< SECOND (Bit 0)                                        */
#define RTC_ALARMB_SECOND_Msk             (0x7fUL)                  /*!< SECOND (Bitfield-Mask: 0x7f)                          */
/* =======================================================  TAMPDATE  ======================================================== */
#define RTC_TAMPDATE_WEEK_Pos             (13UL)                    /*!< WEEK (Bit 13)                                         */
#define RTC_TAMPDATE_WEEK_Msk             (0xe000UL)                /*!< WEEK (Bitfield-Mask: 0x07)                            */
#define RTC_TAMPDATE_MONTH_Pos            (8UL)                     /*!< MONTH (Bit 8)                                         */
#define RTC_TAMPDATE_MONTH_Msk            (0x1f00UL)                /*!< MONTH (Bitfield-Mask: 0x1f)                           */
#define RTC_TAMPDATE_DAY_Pos              (0UL)                     /*!< DAY (Bit 0)                                           */
#define RTC_TAMPDATE_DAY_Msk              (0x3fUL)                  /*!< DAY (Bitfield-Mask: 0x3f)                             */
/* =======================================================  TAMPTIME  ======================================================== */
#define RTC_TAMPTIME_HOUR_Pos             (16UL)                    /*!< HOUR (Bit 16)                                         */
#define RTC_TAMPTIME_HOUR_Msk             (0x3f0000UL)              /*!< HOUR (Bitfield-Mask: 0x3f)                            */
#define RTC_TAMPTIME_MINUTE_Pos           (8UL)                     /*!< MINUTE (Bit 8)                                        */
#define RTC_TAMPTIME_MINUTE_Msk           (0x7f00UL)                /*!< MINUTE (Bitfield-Mask: 0x7f)                          */
#define RTC_TAMPTIME_SECOND_Pos           (0UL)                     /*!< SECOND (Bit 0)                                        */
#define RTC_TAMPTIME_SECOND_Msk           (0x7fUL)                  /*!< SECOND (Bitfield-Mask: 0x7f)                          */
/* ========================================================  AWTARR  ========================================================= */
#define RTC_AWTARR_ARR_Pos                (0UL)                     /*!< ARR (Bit 0)                                           */
#define RTC_AWTARR_ARR_Msk                (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  IER  ========================================================== */
#define RTC_IER_INTERVAL_Pos              (6UL)                     /*!< INTERVAL (Bit 6)                                      */
#define RTC_IER_INTERVAL_Msk              (0x40UL)                  /*!< INTERVAL (Bitfield-Mask: 0x01)                        */
#define RTC_IER_TAMPOV_Pos                (4UL)                     /*!< TAMPOV (Bit 4)                                        */
#define RTC_IER_TAMPOV_Msk                (0x10UL)                  /*!< TAMPOV (Bitfield-Mask: 0x01)                          */
#define RTC_IER_TAMP_Pos                  (3UL)                     /*!< TAMP (Bit 3)                                          */
#define RTC_IER_TAMP_Msk                  (0x8UL)                   /*!< TAMP (Bitfield-Mask: 0x01)                            */
#define RTC_IER_AWTIMER_Pos               (2UL)                     /*!< AWTIMER (Bit 2)                                       */
#define RTC_IER_AWTIMER_Msk               (0x4UL)                   /*!< AWTIMER (Bitfield-Mask: 0x01)                         */
#define RTC_IER_ALARMB_Pos                (1UL)                     /*!< ALARMB (Bit 1)                                        */
#define RTC_IER_ALARMB_Msk                (0x2UL)                   /*!< ALARMB (Bitfield-Mask: 0x01)                          */
#define RTC_IER_ALARMA_Pos                (0UL)                     /*!< ALARMA (Bit 0)                                        */
#define RTC_IER_ALARMA_Msk                (0x1UL)                   /*!< ALARMA (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ISR  ========================================================== */
#define RTC_ISR_INTERVAL_Pos              (6UL)                     /*!< INTERVAL (Bit 6)                                      */
#define RTC_ISR_INTERVAL_Msk              (0x40UL)                  /*!< INTERVAL (Bitfield-Mask: 0x01)                        */
#define RTC_ISR_TAMPOV_Pos                (4UL)                     /*!< TAMPOV (Bit 4)                                        */
#define RTC_ISR_TAMPOV_Msk                (0x10UL)                  /*!< TAMPOV (Bitfield-Mask: 0x01)                          */
#define RTC_ISR_TAMP_Pos                  (3UL)                     /*!< TAMP (Bit 3)                                          */
#define RTC_ISR_TAMP_Msk                  (0x8UL)                   /*!< TAMP (Bitfield-Mask: 0x01)                            */
#define RTC_ISR_AWTIMER_Pos               (2UL)                     /*!< AWTIMER (Bit 2)                                       */
#define RTC_ISR_AWTIMER_Msk               (0x4UL)                   /*!< AWTIMER (Bitfield-Mask: 0x01)                         */
#define RTC_ISR_ALARMB_Pos                (1UL)                     /*!< ALARMB (Bit 1)                                        */
#define RTC_ISR_ALARMB_Msk                (0x2UL)                   /*!< ALARMB (Bitfield-Mask: 0x01)                          */
#define RTC_ISR_ALARMA_Pos                (0UL)                     /*!< ALARMA (Bit 0)                                        */
#define RTC_ISR_ALARMA_Msk                (0x1UL)                   /*!< ALARMA (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
#define RTC_ICR_INTERVAL_Pos              (6UL)                     /*!< INTERVAL (Bit 6)                                      */
#define RTC_ICR_INTERVAL_Msk              (0x40UL)                  /*!< INTERVAL (Bitfield-Mask: 0x01)                        */
#define RTC_ICR_TAMPOV_Pos                (4UL)                     /*!< TAMPOV (Bit 4)                                        */
#define RTC_ICR_TAMPOV_Msk                (0x10UL)                  /*!< TAMPOV (Bitfield-Mask: 0x01)                          */
#define RTC_ICR_TAMP_Pos                  (3UL)                     /*!< TAMP (Bit 3)                                          */
#define RTC_ICR_TAMP_Msk                  (0x8UL)                   /*!< TAMP (Bitfield-Mask: 0x01)                            */
#define RTC_ICR_AWTIMER_Pos               (2UL)                     /*!< AWTIMER (Bit 2)                                       */
#define RTC_ICR_AWTIMER_Msk               (0x4UL)                   /*!< AWTIMER (Bitfield-Mask: 0x01)                         */
#define RTC_ICR_ALARMB_Pos                (1UL)                     /*!< ALARMB (Bit 1)                                        */
#define RTC_ICR_ALARMB_Msk                (0x2UL)                   /*!< ALARMB (Bitfield-Mask: 0x01)                          */
#define RTC_ICR_ALARMA_Pos                (0UL)                     /*!< ALARMA (Bit 0)                                        */
#define RTC_ICR_ALARMA_Msk                (0x1UL)                   /*!< ALARMA (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                            SPI                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define SPIx_CR1_MISOHD_Pos               (18UL)                    /*!< MISOHD (Bit 18)                                       */
#define SPIx_CR1_MISOHD_Msk               (0x40000UL)               /*!< MISOHD (Bitfield-Mask: 0x01)                          */
#define SPIx_CR1_DMATX_Pos                (17UL)                    /*!< DMATX (Bit 17)                                        */
#define SPIx_CR1_DMATX_Msk                (0x20000UL)               /*!< DMATX (Bitfield-Mask: 0x01)                           */
#define SPIx_CR1_DMARX_Pos                (16UL)                    /*!< DMARX (Bit 16)                                        */
#define SPIx_CR1_DMARX_Msk                (0x10000UL)               /*!< DMARX (Bitfield-Mask: 0x01)                           */
#define SPIx_CR1_MODE_Pos                 (14UL)                    /*!< MODE (Bit 14)                                         */
#define SPIx_CR1_MODE_Msk                 (0xc000UL)                /*!< MODE (Bitfield-Mask: 0x03)                            */
#define SPIx_CR1_WIDTH_Pos                (10UL)                    /*!< WIDTH (Bit 10)                                        */
#define SPIx_CR1_WIDTH_Msk                (0x3c00UL)                /*!< WIDTH (Bitfield-Mask: 0x0f)                           */
#define SPIx_CR1_SSM_Pos                  (9UL)                     /*!< SSM (Bit 9)                                           */
#define SPIx_CR1_SSM_Msk                  (0x200UL)                 /*!< SSM (Bitfield-Mask: 0x01)                             */
#define SPIx_CR1_SMP_Pos                  (8UL)                     /*!< SMP (Bit 8)                                           */
#define SPIx_CR1_SMP_Msk                  (0x100UL)                 /*!< SMP (Bitfield-Mask: 0x01)                             */
#define SPIx_CR1_LSBF_Pos                 (7UL)                     /*!< LSBF (Bit 7)                                          */
#define SPIx_CR1_LSBF_Msk                 (0x80UL)                  /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define SPIx_CR1_EN_Pos                   (6UL)                     /*!< EN (Bit 6)                                            */
#define SPIx_CR1_EN_Msk                   (0x40UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define SPIx_CR1_BR_Pos                   (3UL)                     /*!< BR (Bit 3)                                            */
#define SPIx_CR1_BR_Msk                   (0x38UL)                  /*!< BR (Bitfield-Mask: 0x07)                              */
#define SPIx_CR1_MSTR_Pos                 (2UL)                     /*!< MSTR (Bit 2)                                          */
#define SPIx_CR1_MSTR_Msk                 (0x4UL)                   /*!< MSTR (Bitfield-Mask: 0x01)                            */
#define SPIx_CR1_CPOL_Pos                 (1UL)                     /*!< CPOL (Bit 1)                                          */
#define SPIx_CR1_CPOL_Msk                 (0x2UL)                   /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define SPIx_CR1_CPHA_Pos                 (0UL)                     /*!< CPHA (Bit 0)                                          */
#define SPIx_CR1_CPHA_Msk                 (0x1UL)                   /*!< CPHA (Bitfield-Mask: 0x01)                            */
/* ==========================================================  IER  ========================================================== */
#define SPIx_IER_MODF_Pos                 (7UL)                     /*!< MODF (Bit 7)                                          */
#define SPIx_IER_MODF_Msk                 (0x80UL)                  /*!< MODF (Bitfield-Mask: 0x01)                            */
#define SPIx_IER_SSERR_Pos                (6UL)                     /*!< SSERR (Bit 6)                                         */
#define SPIx_IER_SSERR_Msk                (0x40UL)                  /*!< SSERR (Bitfield-Mask: 0x01)                           */
#define SPIx_IER_OV_Pos                   (5UL)                     /*!< OV (Bit 5)                                            */
#define SPIx_IER_OV_Msk                   (0x20UL)                  /*!< OV (Bitfield-Mask: 0x01)                              */
#define SPIx_IER_UD_Pos                   (4UL)                     /*!< UD (Bit 4)                                            */
#define SPIx_IER_UD_Msk                   (0x10UL)                  /*!< UD (Bitfield-Mask: 0x01)                              */
#define SPIx_IER_SSR_Pos                  (3UL)                     /*!< SSR (Bit 3)                                           */
#define SPIx_IER_SSR_Msk                  (0x8UL)                   /*!< SSR (Bitfield-Mask: 0x01)                             */
#define SPIx_IER_SSF_Pos                  (2UL)                     /*!< SSF (Bit 2)                                           */
#define SPIx_IER_SSF_Msk                  (0x4UL)                   /*!< SSF (Bitfield-Mask: 0x01)                             */
#define SPIx_IER_RXNE_Pos                 (1UL)                     /*!< RXNE (Bit 1)                                          */
#define SPIx_IER_RXNE_Msk                 (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define SPIx_IER_TXE_Pos                  (0UL)                     /*!< TXE (Bit 0)                                           */
#define SPIx_IER_TXE_Msk                  (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CR2  ========================================================== */
#define SPIx_CR2_HDOE_Pos                 (0UL)                     /*!< HDOE (Bit 0)                                          */
#define SPIx_CR2_HDOE_Msk                 (0x1UL)                   /*!< HDOE (Bitfield-Mask: 0x01)                            */
/* ==========================================================  SSI  ========================================================== */
#define SPIx_SSI_SSI_Pos                  (0UL)                     /*!< SSI (Bit 0)                                           */
#define SPIx_SSI_SSI_Msk                  (0x1UL)                   /*!< SSI (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define SPIx_ISR_SSLVL_Pos                (9UL)                     /*!< SSLVL (Bit 9)                                         */
#define SPIx_ISR_SSLVL_Msk                (0x200UL)                 /*!< SSLVL (Bitfield-Mask: 0x01)                           */
#define SPIx_ISR_BUSY_Pos                 (8UL)                     /*!< BUSY (Bit 8)                                          */
#define SPIx_ISR_BUSY_Msk                 (0x100UL)                 /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define SPIx_ISR_MODF_Pos                 (7UL)                     /*!< MODF (Bit 7)                                          */
#define SPIx_ISR_MODF_Msk                 (0x80UL)                  /*!< MODF (Bitfield-Mask: 0x01)                            */
#define SPIx_ISR_SSERR_Pos                (6UL)                     /*!< SSERR (Bit 6)                                         */
#define SPIx_ISR_SSERR_Msk                (0x40UL)                  /*!< SSERR (Bitfield-Mask: 0x01)                           */
#define SPIx_ISR_OV_Pos                   (5UL)                     /*!< OV (Bit 5)                                            */
#define SPIx_ISR_OV_Msk                   (0x20UL)                  /*!< OV (Bitfield-Mask: 0x01)                              */
#define SPIx_ISR_UD_Pos                   (4UL)                     /*!< UD (Bit 4)                                            */
#define SPIx_ISR_UD_Msk                   (0x10UL)                  /*!< UD (Bitfield-Mask: 0x01)                              */
#define SPIx_ISR_SSR_Pos                  (3UL)                     /*!< SSR (Bit 3)                                           */
#define SPIx_ISR_SSR_Msk                  (0x8UL)                   /*!< SSR (Bitfield-Mask: 0x01)                             */
#define SPIx_ISR_SSF_Pos                  (2UL)                     /*!< SSF (Bit 2)                                           */
#define SPIx_ISR_SSF_Msk                  (0x4UL)                   /*!< SSF (Bitfield-Mask: 0x01)                             */
#define SPIx_ISR_RXNE_Pos                 (1UL)                     /*!< RXNE (Bit 1)                                          */
#define SPIx_ISR_RXNE_Msk                 (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define SPIx_ISR_TXE_Pos                  (0UL)                     /*!< TXE (Bit 0)                                           */
#define SPIx_ISR_TXE_Msk                  (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define SPIx_ICR_MODF_Pos                 (7UL)                     /*!< MODF (Bit 7)                                          */
#define SPIx_ICR_MODF_Msk                 (0x80UL)                  /*!< MODF (Bitfield-Mask: 0x01)                            */
#define SPIx_ICR_SSERR_Pos                (6UL)                     /*!< SSERR (Bit 6)                                         */
#define SPIx_ICR_SSERR_Msk                (0x40UL)                  /*!< SSERR (Bitfield-Mask: 0x01)                           */
#define SPIx_ICR_OV_Pos                   (5UL)                     /*!< OV (Bit 5)                                            */
#define SPIx_ICR_OV_Msk                   (0x20UL)                  /*!< OV (Bitfield-Mask: 0x01)                              */
#define SPIx_ICR_UD_Pos                   (4UL)                     /*!< UD (Bit 4)                                            */
#define SPIx_ICR_UD_Msk                   (0x10UL)                  /*!< UD (Bitfield-Mask: 0x01)                              */
#define SPIx_ICR_SSR_Pos                  (3UL)                     /*!< SSR (Bit 3)                                           */
#define SPIx_ICR_SSR_Msk                  (0x8UL)                   /*!< SSR (Bitfield-Mask: 0x01)                             */
#define SPIx_ICR_SSF_Pos                  (2UL)                     /*!< SSF (Bit 2)                                           */
#define SPIx_ICR_SSF_Msk                  (0x4UL)                   /*!< SSF (Bitfield-Mask: 0x01)                             */
#define SPIx_ICR_RXNE_Pos                 (1UL)                     /*!< RXNE (Bit 1)                                          */
#define SPIx_ICR_RXNE_Msk                 (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define SPIx_ICR_FLUSH_Pos                (0UL)                     /*!< FLUSH (Bit 0)                                         */
#define SPIx_ICR_FLUSH_Msk                (0x1UL)                   /*!< FLUSH (Bitfield-Mask: 0x01)                           */
/* ==========================================================  DR  =========================================================== */
#define SPIx_DR_DR_Pos                    (0UL)                     /*!< DR (Bit 0)                                            */
#define SPIx_DR_DR_Msk                    (0xffffUL)                /*!< DR (Bitfield-Mask: 0xffff)                            */


/* =========================================================================================================================== */
/* ================                                          SYSCTRL                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define SYSCTRL_CR0_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_CR0_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_CR0_HCLKPRS_Pos           (5UL)                     /*!< HCLKPRS (Bit 5)                                       */
#define SYSCTRL_CR0_HCLKPRS_Msk           (0xe0UL)                  /*!< HCLKPRS (Bitfield-Mask: 0x07)                         */
#define SYSCTRL_CR0_PCLKPRS_Pos           (3UL)                     /*!< PCLKPRS (Bit 3)                                       */
#define SYSCTRL_CR0_PCLKPRS_Msk           (0x18UL)                  /*!< PCLKPRS (Bitfield-Mask: 0x03)                         */
#define SYSCTRL_CR0_SYSCLK_Pos            (0UL)                     /*!< SYSCLK (Bit 0)                                        */
#define SYSCTRL_CR0_SYSCLK_Msk            (0x7UL)                   /*!< SYSCLK (Bitfield-Mask: 0x07)                          */
/* ==========================================================  CR1  ========================================================== */
#define SYSCTRL_CR1_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_CR1_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_CR1_CLKCCS_Pos            (8UL)                     /*!< CLKCCS (Bit 8)                                        */
#define SYSCTRL_CR1_CLKCCS_Msk            (0x100UL)                 /*!< CLKCCS (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_CR1_HSECCS_Pos            (7UL)                     /*!< HSECCS (Bit 7)                                        */
#define SYSCTRL_CR1_HSECCS_Msk            (0x80UL)                  /*!< HSECCS (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_CR1_LSECCS_Pos            (6UL)                     /*!< LSECCS (Bit 6)                                        */
#define SYSCTRL_CR1_LSECCS_Msk            (0x40UL)                  /*!< LSECCS (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_CR1_LSELOCK_Pos           (5UL)                     /*!< LSELOCK (Bit 5)                                       */
#define SYSCTRL_CR1_LSELOCK_Msk           (0x20UL)                  /*!< LSELOCK (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_CR1_LSEEN_Pos             (4UL)                     /*!< LSEEN (Bit 4)                                         */
#define SYSCTRL_CR1_LSEEN_Msk             (0x10UL)                  /*!< LSEEN (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_CR1_LSIEN_Pos             (3UL)                     /*!< LSIEN (Bit 3)                                         */
#define SYSCTRL_CR1_LSIEN_Msk             (0x8UL)                   /*!< LSIEN (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_CR1_PLLEN_Pos             (2UL)                     /*!< PLLEN (Bit 2)                                         */
#define SYSCTRL_CR1_PLLEN_Msk             (0x4UL)                   /*!< PLLEN (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_CR1_HSEEN_Pos             (1UL)                     /*!< HSEEN (Bit 1)                                         */
#define SYSCTRL_CR1_HSEEN_Msk             (0x2UL)                   /*!< HSEEN (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_CR1_HSIEN_Pos             (0UL)                     /*!< HSIEN (Bit 0)                                         */
#define SYSCTRL_CR1_HSIEN_Msk             (0x1UL)                   /*!< HSIEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CR2  ========================================================== */
#define SYSCTRL_CR2_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_CR2_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_CR2_WAKEUPCLK_Pos         (3UL)                     /*!< WAKEUPCLK (Bit 3)                                     */
#define SYSCTRL_CR2_WAKEUPCLK_Msk         (0x8UL)                   /*!< WAKEUPCLK (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_CR2_LOCKUP_Pos            (2UL)                     /*!< LOCKUP (Bit 2)                                        */
#define SYSCTRL_CR2_LOCKUP_Msk            (0x4UL)                   /*!< LOCKUP (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_CR2_SWDIO_Pos             (1UL)                     /*!< SWDIO (Bit 1)                                         */
#define SYSCTRL_CR2_SWDIO_Msk             (0x2UL)                   /*!< SWDIO (Bitfield-Mask: 0x01)                           */
/* ==========================================================  IER  ========================================================== */
#define SYSCTRL_IER_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_IER_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_IER_HSEFAULT_Pos          (8UL)                     /*!< HSEFAULT (Bit 8)                                      */
#define SYSCTRL_IER_HSEFAULT_Msk          (0x100UL)                 /*!< HSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_IER_LSEFAULT_Pos          (7UL)                     /*!< LSEFAULT (Bit 7)                                      */
#define SYSCTRL_IER_LSEFAULT_Msk          (0x80UL)                  /*!< LSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_IER_HSEFAIL_Pos           (6UL)                     /*!< HSEFAIL (Bit 6)                                       */
#define SYSCTRL_IER_HSEFAIL_Msk           (0x40UL)                  /*!< HSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_IER_LSEFAIL_Pos           (5UL)                     /*!< LSEFAIL (Bit 5)                                       */
#define SYSCTRL_IER_LSEFAIL_Msk           (0x20UL)                  /*!< LSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_IER_LSERDY_Pos            (4UL)                     /*!< LSERDY (Bit 4)                                        */
#define SYSCTRL_IER_LSERDY_Msk            (0x10UL)                  /*!< LSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_IER_LSIRDY_Pos            (3UL)                     /*!< LSIRDY (Bit 3)                                        */
#define SYSCTRL_IER_LSIRDY_Msk            (0x8UL)                   /*!< LSIRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_IER_PLLRDY_Pos            (2UL)                     /*!< PLLRDY (Bit 2)                                        */
#define SYSCTRL_IER_PLLRDY_Msk            (0x4UL)                   /*!< PLLRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_IER_HSERDY_Pos            (1UL)                     /*!< HSERDY (Bit 1)                                        */
#define SYSCTRL_IER_HSERDY_Msk            (0x2UL)                   /*!< HSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_IER_HSIRDY_Pos            (0UL)                     /*!< HSIRDY (Bit 0)                                        */
#define SYSCTRL_IER_HSIRDY_Msk            (0x1UL)                   /*!< HSIRDY (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ISR  ========================================================== */
#define SYSCTRL_ISR_LSESTABLE_Pos         (15UL)                    /*!< LSESTABLE (Bit 15)                                    */
#define SYSCTRL_ISR_LSESTABLE_Msk         (0x8000UL)                /*!< LSESTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_LSISTABLE_Pos         (14UL)                    /*!< LSISTABLE (Bit 14)                                    */
#define SYSCTRL_ISR_LSISTABLE_Msk         (0x4000UL)                /*!< LSISTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_PLLSTABLE_Pos         (13UL)                    /*!< PLLSTABLE (Bit 13)                                    */
#define SYSCTRL_ISR_PLLSTABLE_Msk         (0x2000UL)                /*!< PLLSTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_HSESTABLE_Pos         (12UL)                    /*!< HSESTABLE (Bit 12)                                    */
#define SYSCTRL_ISR_HSESTABLE_Msk         (0x1000UL)                /*!< HSESTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_HSISTABLE_Pos         (11UL)                    /*!< HSISTABLE (Bit 11)                                    */
#define SYSCTRL_ISR_HSISTABLE_Msk         (0x800UL)                 /*!< HSISTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_HSEFAULT_Pos          (8UL)                     /*!< HSEFAULT (Bit 8)                                      */
#define SYSCTRL_ISR_HSEFAULT_Msk          (0x100UL)                 /*!< HSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_ISR_LSEFAULT_Pos          (7UL)                     /*!< LSEFAULT (Bit 7)                                      */
#define SYSCTRL_ISR_LSEFAULT_Msk          (0x80UL)                  /*!< LSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_ISR_HSEFAIL_Pos           (6UL)                     /*!< HSEFAIL (Bit 6)                                       */
#define SYSCTRL_ISR_HSEFAIL_Msk           (0x40UL)                  /*!< HSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_ISR_LSEFAIL_Pos           (5UL)                     /*!< LSEFAIL (Bit 5)                                       */
#define SYSCTRL_ISR_LSEFAIL_Msk           (0x20UL)                  /*!< LSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_ISR_LSERDY_Pos            (4UL)                     /*!< LSERDY (Bit 4)                                        */
#define SYSCTRL_ISR_LSERDY_Msk            (0x10UL)                  /*!< LSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ISR_LSIRDY_Pos            (3UL)                     /*!< LSIRDY (Bit 3)                                        */
#define SYSCTRL_ISR_LSIRDY_Msk            (0x8UL)                   /*!< LSIRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ISR_PLLRDY_Pos            (2UL)                     /*!< PLLRDY (Bit 2)                                        */
#define SYSCTRL_ISR_PLLRDY_Msk            (0x4UL)                   /*!< PLLRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ISR_HSERDY_Pos            (1UL)                     /*!< HSERDY (Bit 1)                                        */
#define SYSCTRL_ISR_HSERDY_Msk            (0x2UL)                   /*!< HSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ISR_HSIRDY_Pos            (0UL)                     /*!< HSIRDY (Bit 0)                                        */
#define SYSCTRL_ISR_HSIRDY_Msk            (0x1UL)                   /*!< HSIRDY (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
#define SYSCTRL_ICR_HSEFAULT_Pos          (8UL)                     /*!< HSEFAULT (Bit 8)                                      */
#define SYSCTRL_ICR_HSEFAULT_Msk          (0x100UL)                 /*!< HSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_ICR_LSEFAULT_Pos          (7UL)                     /*!< LSEFAULT (Bit 7)                                      */
#define SYSCTRL_ICR_LSEFAULT_Msk          (0x80UL)                  /*!< LSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_ICR_HSEFAIL_Pos           (6UL)                     /*!< HSEFAIL (Bit 6)                                       */
#define SYSCTRL_ICR_HSEFAIL_Msk           (0x40UL)                  /*!< HSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_ICR_LSEFAIL_Pos           (5UL)                     /*!< LSEFAIL (Bit 5)                                       */
#define SYSCTRL_ICR_LSEFAIL_Msk           (0x20UL)                  /*!< LSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_ICR_LSERDY_Pos            (4UL)                     /*!< LSERDY (Bit 4)                                        */
#define SYSCTRL_ICR_LSERDY_Msk            (0x10UL)                  /*!< LSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ICR_LSIRDY_Pos            (3UL)                     /*!< LSIRDY (Bit 3)                                        */
#define SYSCTRL_ICR_LSIRDY_Msk            (0x8UL)                   /*!< LSIRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ICR_PLLRDY_Pos            (2UL)                     /*!< PLLRDY (Bit 2)                                        */
#define SYSCTRL_ICR_PLLRDY_Msk            (0x4UL)                   /*!< PLLRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ICR_HSERDY_Pos            (1UL)                     /*!< HSERDY (Bit 1)                                        */
#define SYSCTRL_ICR_HSERDY_Msk            (0x2UL)                   /*!< HSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ICR_HSIRDY_Pos            (0UL)                     /*!< HSIRDY (Bit 0)                                        */
#define SYSCTRL_ICR_HSIRDY_Msk            (0x1UL)                   /*!< HSIRDY (Bitfield-Mask: 0x01)                          */
/* ==========================================================  HSI  ========================================================== */
#define SYSCTRL_HSI_STABLE_Pos            (15UL)                    /*!< STABLE (Bit 15)                                       */
#define SYSCTRL_HSI_STABLE_Msk            (0x8000UL)                /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_HSI_DIV_Pos               (11UL)                    /*!< DIV (Bit 11)                                          */
#define SYSCTRL_HSI_DIV_Msk               (0x7800UL)                /*!< DIV (Bitfield-Mask: 0x0f)                             */
#define SYSCTRL_HSI_TRIM_Pos              (0UL)                     /*!< TRIM (Bit 0)                                          */
#define SYSCTRL_HSI_TRIM_Msk              (0x7ffUL)                 /*!< TRIM (Bitfield-Mask: 0x7ff)                           */
/* ==========================================================  HSE  ========================================================== */
#define SYSCTRL_HSE_STABLE_Pos            (19UL)                    /*!< STABLE (Bit 19)                                       */
#define SYSCTRL_HSE_STABLE_Msk            (0x80000UL)               /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_HSE_DETCNT_Pos            (8UL)                     /*!< DETCNT (Bit 8)                                        */
#define SYSCTRL_HSE_DETCNT_Msk            (0x7ff00UL)               /*!< DETCNT (Bitfield-Mask: 0x7ff)                         */
#define SYSCTRL_HSE_FLT_Pos               (7UL)                     /*!< FLT (Bit 7)                                           */
#define SYSCTRL_HSE_FLT_Msk               (0x80UL)                  /*!< FLT (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_HSE_MODE_Pos              (6UL)                     /*!< MODE (Bit 6)                                          */
#define SYSCTRL_HSE_MODE_Msk              (0x40UL)                  /*!< MODE (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_HSE_WAITCYCLE_Pos         (4UL)                     /*!< WAITCYCLE (Bit 4)                                     */
#define SYSCTRL_HSE_WAITCYCLE_Msk         (0x30UL)                  /*!< WAITCYCLE (Bitfield-Mask: 0x03)                       */
#define SYSCTRL_HSE_FREQ_Pos              (2UL)                     /*!< FREQ (Bit 2)                                          */
#define SYSCTRL_HSE_FREQ_Msk              (0xcUL)                   /*!< FREQ (Bitfield-Mask: 0x03)                            */
#define SYSCTRL_HSE_DRIVER_Pos            (0UL)                     /*!< DRIVER (Bit 0)                                        */
#define SYSCTRL_HSE_DRIVER_Msk            (0x3UL)                   /*!< DRIVER (Bitfield-Mask: 0x03)                          */
/* ==========================================================  LSI  ========================================================== */
#define SYSCTRL_LSI_STABLE_Pos            (15UL)                    /*!< STABLE (Bit 15)                                       */
#define SYSCTRL_LSI_STABLE_Msk            (0x8000UL)                /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_LSI_WAITCYCLE_Pos         (10UL)                    /*!< WAITCYCLE (Bit 10)                                    */
#define SYSCTRL_LSI_WAITCYCLE_Msk         (0xc00UL)                 /*!< WAITCYCLE (Bitfield-Mask: 0x03)                       */
#define SYSCTRL_LSI_TRIM_Pos              (0UL)                     /*!< TRIM (Bit 0)                                          */
#define SYSCTRL_LSI_TRIM_Msk              (0x3ffUL)                 /*!< TRIM (Bitfield-Mask: 0x3ff)                           */
/* ==========================================================  LSE  ========================================================== */
#define SYSCTRL_LSE_STABLE_Pos            (15UL)                    /*!< STABLE (Bit 15)                                       */
#define SYSCTRL_LSE_STABLE_Msk            (0x8000UL)                /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_LSE_MODE_Pos              (6UL)                     /*!< MODE (Bit 6)                                          */
#define SYSCTRL_LSE_MODE_Msk              (0x40UL)                  /*!< MODE (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_LSE_WAITCYCLE_Pos         (4UL)                     /*!< WAITCYCLE (Bit 4)                                     */
#define SYSCTRL_LSE_WAITCYCLE_Msk         (0x30UL)                  /*!< WAITCYCLE (Bitfield-Mask: 0x03)                       */
#define SYSCTRL_LSE_AMP_Pos               (2UL)                     /*!< AMP (Bit 2)                                           */
#define SYSCTRL_LSE_AMP_Msk               (0xcUL)                   /*!< AMP (Bitfield-Mask: 0x03)                             */
#define SYSCTRL_LSE_DRIVER_Pos            (0UL)                     /*!< DRIVER (Bit 0)                                        */
#define SYSCTRL_LSE_DRIVER_Msk            (0x3UL)                   /*!< DRIVER (Bitfield-Mask: 0x03)                          */
/* ==========================================================  PLL  ========================================================== */
#define SYSCTRL_PLL_RFU_Pos               (16UL)                    /*!< RFU (Bit 16)                                          */
#define SYSCTRL_PLL_RFU_Msk               (0xf0000UL)               /*!< RFU (Bitfield-Mask: 0x0f)                             */
#define SYSCTRL_PLL_STABLE_Pos            (15UL)                    /*!< STABLE (Bit 15)                                       */
#define SYSCTRL_PLL_STABLE_Msk            (0x8000UL)                /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_PLL_WAITCYCLE_Pos         (12UL)                    /*!< WAITCYCLE (Bit 12)                                    */
#define SYSCTRL_PLL_WAITCYCLE_Msk         (0x7000UL)                /*!< WAITCYCLE (Bitfield-Mask: 0x07)                       */
#define SYSCTRL_PLL_FREQOUT_Pos           (9UL)                     /*!< FREQOUT (Bit 9)                                       */
#define SYSCTRL_PLL_FREQOUT_Msk           (0xe00UL)                 /*!< FREQOUT (Bitfield-Mask: 0x07)                         */
#define SYSCTRL_PLL_MUL_Pos               (4UL)                     /*!< MUL (Bit 4)                                           */
#define SYSCTRL_PLL_MUL_Msk               (0x1f0UL)                 /*!< MUL (Bitfield-Mask: 0x1f)                             */
#define SYSCTRL_PLL_FREQIN_Pos            (2UL)                     /*!< FREQIN (Bit 2)                                        */
#define SYSCTRL_PLL_FREQIN_Msk            (0xcUL)                   /*!< FREQIN (Bitfield-Mask: 0x03)                          */
#define SYSCTRL_PLL_SOURCE_Pos            (0UL)                     /*!< SOURCE (Bit 0)                                        */
#define SYSCTRL_PLL_SOURCE_Msk            (0x3UL)                   /*!< SOURCE (Bitfield-Mask: 0x03)                          */
/* =========================================================  DEBUG  ========================================================= */
#define SYSCTRL_DEBUG_WWDT_Pos            (10UL)                    /*!< WWDT (Bit 10)                                         */
#define SYSCTRL_DEBUG_WWDT_Msk            (0x400UL)                 /*!< WWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_DEBUG_IWDT_Pos            (9UL)                     /*!< IWDT (Bit 9)                                          */
#define SYSCTRL_DEBUG_IWDT_Msk            (0x200UL)                 /*!< IWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_DEBUG_RTC_Pos             (8UL)                     /*!< RTC (Bit 8)                                           */
#define SYSCTRL_DEBUG_RTC_Msk             (0x100UL)                 /*!< RTC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_DEBUG_AWT_Pos             (6UL)                     /*!< AWT (Bit 6)                                           */
#define SYSCTRL_DEBUG_AWT_Msk             (0x40UL)                  /*!< AWT (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_DEBUG_BTIM123_Pos         (5UL)                     /*!< BTIM123 (Bit 5)                                       */
#define SYSCTRL_DEBUG_BTIM123_Msk         (0x20UL)                  /*!< BTIM123 (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_DEBUG_GTIM4_Pos           (4UL)                     /*!< GTIM4 (Bit 4)                                         */
#define SYSCTRL_DEBUG_GTIM4_Msk           (0x10UL)                  /*!< GTIM4 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_GTIM3_Pos           (3UL)                     /*!< GTIM3 (Bit 3)                                         */
#define SYSCTRL_DEBUG_GTIM3_Msk           (0x8UL)                   /*!< GTIM3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_GTIM2_Pos           (2UL)                     /*!< GTIM2 (Bit 2)                                         */
#define SYSCTRL_DEBUG_GTIM2_Msk           (0x4UL)                   /*!< GTIM2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_GTIM1_Pos           (1UL)                     /*!< GTIM1 (Bit 1)                                         */
#define SYSCTRL_DEBUG_GTIM1_Msk           (0x2UL)                   /*!< GTIM1 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_ATIM_Pos            (0UL)                     /*!< ATIM (Bit 0)                                          */
#define SYSCTRL_DEBUG_ATIM_Msk            (0x1UL)                   /*!< ATIM (Bitfield-Mask: 0x01)                            */
/* =========================================================  AHBEN  ========================================================= */
#define SYSCTRL_AHBEN_GPIOF_Pos           (9UL)                     /*!< GPIOF (Bit 9)                                         */
#define SYSCTRL_AHBEN_GPIOF_Msk           (0x200UL)                 /*!< GPIOF (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_GPIOC_Pos           (6UL)                     /*!< GPIOC (Bit 6)                                         */
#define SYSCTRL_AHBEN_GPIOC_Msk           (0x40UL)                  /*!< GPIOC (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_GPIOB_Pos           (5UL)                     /*!< GPIOB (Bit 5)                                         */
#define SYSCTRL_AHBEN_GPIOB_Msk           (0x20UL)                  /*!< GPIOB (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_GPIOA_Pos           (4UL)                     /*!< GPIOA (Bit 4)                                         */
#define SYSCTRL_AHBEN_GPIOA_Msk           (0x10UL)                  /*!< GPIOA (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_CRC_Pos             (2UL)                     /*!< CRC (Bit 2)                                           */
#define SYSCTRL_AHBEN_CRC_Msk             (0x4UL)                   /*!< CRC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_AHBEN_FLASH_Pos           (1UL)                     /*!< FLASH (Bit 1)                                         */
#define SYSCTRL_AHBEN_FLASH_Msk           (0x2UL)                   /*!< FLASH (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_DMA_Pos             (0UL)                     /*!< DMA (Bit 0)                                           */
#define SYSCTRL_AHBEN_DMA_Msk             (0x1UL)                   /*!< DMA (Bitfield-Mask: 0x01)                             */
/* ========================================================  APBEN2  ========================================================= */
#define SYSCTRL_APBEN2_AWT_Pos            (13UL)                    /*!< AWT (Bit 13)                                          */
#define SYSCTRL_APBEN2_AWT_Msk            (0x2000UL)                /*!< AWT (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_APBEN2_BTIM_Pos           (12UL)                    /*!< BTIM (Bit 12)                                         */
#define SYSCTRL_APBEN2_BTIM_Msk           (0x1000UL)                /*!< BTIM (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN2_GTIM4_Pos          (11UL)                    /*!< GTIM4 (Bit 11)                                        */
#define SYSCTRL_APBEN2_GTIM4_Msk          (0x800UL)                 /*!< GTIM4 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN2_GTIM3_Pos          (10UL)                    /*!< GTIM3 (Bit 10)                                        */
#define SYSCTRL_APBEN2_GTIM3_Msk          (0x400UL)                 /*!< GTIM3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN2_UART1_Pos          (9UL)                     /*!< UART1 (Bit 9)                                         */
#define SYSCTRL_APBEN2_UART1_Msk          (0x200UL)                 /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN2_SPI1_Pos           (8UL)                     /*!< SPI1 (Bit 8)                                          */
#define SYSCTRL_APBEN2_SPI1_Msk           (0x100UL)                 /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN2_ATIM_Pos           (7UL)                     /*!< ATIM (Bit 7)                                          */
#define SYSCTRL_APBEN2_ATIM_Msk           (0x80UL)                  /*!< ATIM (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN2_VC_Pos             (4UL)                     /*!< VC (Bit 4)                                            */
#define SYSCTRL_APBEN2_VC_Msk             (0x10UL)                  /*!< VC (Bitfield-Mask: 0x01)                              */
#define SYSCTRL_APBEN2_ADC_Pos            (2UL)                     /*!< ADC (Bit 2)                                           */
#define SYSCTRL_APBEN2_ADC_Msk            (0x4UL)                   /*!< ADC (Bitfield-Mask: 0x01)                             */
/* ========================================================  APBEN1  ========================================================= */
#define SYSCTRL_APBEN1_I2C2_Pos           (12UL)                    /*!< I2C2 (Bit 12)                                         */
#define SYSCTRL_APBEN1_I2C2_Msk           (0x1000UL)                /*!< I2C2 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_I2C1_Pos           (11UL)                    /*!< I2C1 (Bit 11)                                         */
#define SYSCTRL_APBEN1_I2C1_Msk           (0x800UL)                 /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_UART3_Pos          (8UL)                     /*!< UART3 (Bit 8)                                         */
#define SYSCTRL_APBEN1_UART3_Msk          (0x100UL)                 /*!< UART3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_UART2_Pos          (7UL)                     /*!< UART2 (Bit 7)                                         */
#define SYSCTRL_APBEN1_UART2_Msk          (0x80UL)                  /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_SPI2_Pos           (6UL)                     /*!< SPI2 (Bit 6)                                          */
#define SYSCTRL_APBEN1_SPI2_Msk           (0x40UL)                  /*!< SPI2 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_IWDT_Pos           (5UL)                     /*!< IWDT (Bit 5)                                          */
#define SYSCTRL_APBEN1_IWDT_Msk           (0x20UL)                  /*!< IWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_WWDT_Pos           (4UL)                     /*!< WWDT (Bit 4)                                          */
#define SYSCTRL_APBEN1_WWDT_Msk           (0x10UL)                  /*!< WWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_RTC_Pos            (3UL)                     /*!< RTC (Bit 3)                                           */
#define SYSCTRL_APBEN1_RTC_Msk            (0x8UL)                   /*!< RTC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_APBEN1_GTIM2_Pos          (2UL)                     /*!< GTIM2 (Bit 2)                                         */
#define SYSCTRL_APBEN1_GTIM2_Msk          (0x4UL)                   /*!< GTIM2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_GTIM1_Pos          (1UL)                     /*!< GTIM1 (Bit 1)                                         */
#define SYSCTRL_APBEN1_GTIM1_Msk          (0x2UL)                   /*!< GTIM1 (Bitfield-Mask: 0x01)                           */
/* ========================================================  AHBRST  ========================================================= */
#define SYSCTRL_AHBRST_GPIOF_Pos          (9UL)                     /*!< GPIOF (Bit 9)                                         */
#define SYSCTRL_AHBRST_GPIOF_Msk          (0x200UL)                 /*!< GPIOF (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_GPIOC_Pos          (6UL)                     /*!< GPIOC (Bit 6)                                         */
#define SYSCTRL_AHBRST_GPIOC_Msk          (0x40UL)                  /*!< GPIOC (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_GPIOB_Pos          (5UL)                     /*!< GPIOB (Bit 5)                                         */
#define SYSCTRL_AHBRST_GPIOB_Msk          (0x20UL)                  /*!< GPIOB (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_GPIOA_Pos          (4UL)                     /*!< GPIOA (Bit 4)                                         */
#define SYSCTRL_AHBRST_GPIOA_Msk          (0x10UL)                  /*!< GPIOA (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_CRC_Pos            (2UL)                     /*!< CRC (Bit 2)                                           */
#define SYSCTRL_AHBRST_CRC_Msk            (0x4UL)                   /*!< CRC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_AHBRST_FLASH_Pos          (1UL)                     /*!< FLASH (Bit 1)                                         */
#define SYSCTRL_AHBRST_FLASH_Msk          (0x2UL)                   /*!< FLASH (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_DMA_Pos            (0UL)                     /*!< DMA (Bit 0)                                           */
#define SYSCTRL_AHBRST_DMA_Msk            (0x1UL)                   /*!< DMA (Bitfield-Mask: 0x01)                             */
/* ========================================================  APBRST2  ======================================================== */
#define SYSCTRL_APBRST2_AWT_Pos           (13UL)                    /*!< AWT (Bit 13)                                          */
#define SYSCTRL_APBRST2_AWT_Msk           (0x2000UL)                /*!< AWT (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_APBRST2_BTIM_Pos          (12UL)                    /*!< BTIM (Bit 12)                                         */
#define SYSCTRL_APBRST2_BTIM_Msk          (0x1000UL)                /*!< BTIM (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST2_GTIM4_Pos         (11UL)                    /*!< GTIM4 (Bit 11)                                        */
#define SYSCTRL_APBRST2_GTIM4_Msk         (0x800UL)                 /*!< GTIM4 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST2_GTIM3_Pos         (10UL)                    /*!< GTIM3 (Bit 10)                                        */
#define SYSCTRL_APBRST2_GTIM3_Msk         (0x400UL)                 /*!< GTIM3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST2_UART1_Pos         (9UL)                     /*!< UART1 (Bit 9)                                         */
#define SYSCTRL_APBRST2_UART1_Msk         (0x200UL)                 /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST2_SPI1_Pos          (8UL)                     /*!< SPI1 (Bit 8)                                          */
#define SYSCTRL_APBRST2_SPI1_Msk          (0x100UL)                 /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST2_ATIM_Pos          (7UL)                     /*!< ATIM (Bit 7)                                          */
#define SYSCTRL_APBRST2_ATIM_Msk          (0x80UL)                  /*!< ATIM (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST2_VC_Pos            (4UL)                     /*!< VC (Bit 4)                                            */
#define SYSCTRL_APBRST2_VC_Msk            (0x10UL)                  /*!< VC (Bitfield-Mask: 0x01)                              */
#define SYSCTRL_APBRST2_ADC_Pos           (2UL)                     /*!< ADC (Bit 2)                                           */
#define SYSCTRL_APBRST2_ADC_Msk           (0x4UL)                   /*!< ADC (Bitfield-Mask: 0x01)                             */
/* ========================================================  APBRST1  ======================================================== */
#define SYSCTRL_APBRST1_I2C2_Pos          (12UL)                    /*!< I2C2 (Bit 12)                                         */
#define SYSCTRL_APBRST1_I2C2_Msk          (0x1000UL)                /*!< I2C2 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_I2C1_Pos          (11UL)                    /*!< I2C1 (Bit 11)                                         */
#define SYSCTRL_APBRST1_I2C1_Msk          (0x800UL)                 /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_UART3_Pos         (8UL)                     /*!< UART3 (Bit 8)                                         */
#define SYSCTRL_APBRST1_UART3_Msk         (0x100UL)                 /*!< UART3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_UART2_Pos         (7UL)                     /*!< UART2 (Bit 7)                                         */
#define SYSCTRL_APBRST1_UART2_Msk         (0x80UL)                  /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_SPI2_Pos          (6UL)                     /*!< SPI2 (Bit 6)                                          */
#define SYSCTRL_APBRST1_SPI2_Msk          (0x40UL)                  /*!< SPI2 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_IWDT_Pos          (5UL)                     /*!< IWDT (Bit 5)                                          */
#define SYSCTRL_APBRST1_IWDT_Msk          (0x20UL)                  /*!< IWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_WWDT_Pos          (4UL)                     /*!< WWDT (Bit 4)                                          */
#define SYSCTRL_APBRST1_WWDT_Msk          (0x10UL)                  /*!< WWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_RTC_Pos           (3UL)                     /*!< RTC (Bit 3)                                           */
#define SYSCTRL_APBRST1_RTC_Msk           (0x8UL)                   /*!< RTC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_APBRST1_GTIM2_Pos         (2UL)                     /*!< GTIM2 (Bit 2)                                         */
#define SYSCTRL_APBRST1_GTIM2_Msk         (0x4UL)                   /*!< GTIM2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_GTIM1_Pos         (1UL)                     /*!< GTIM1 (Bit 1)                                         */
#define SYSCTRL_APBRST1_GTIM1_Msk         (0x2UL)                   /*!< GTIM1 (Bitfield-Mask: 0x01)                           */
/* =======================================================  RESETFLAG  ======================================================= */
#define SYSCTRL_RESETFLAG_SYSRESETREQ_Pos (9UL)                     /*!< SYSRESETREQ (Bit 9)                                   */
#define SYSCTRL_RESETFLAG_SYSRESETREQ_Msk (0x200UL)                 /*!< SYSRESETREQ (Bitfield-Mask: 0x01)                     */
#define SYSCTRL_RESETFLAG_LOCKUP_Pos      (8UL)                     /*!< LOCKUP (Bit 8)                                        */
#define SYSCTRL_RESETFLAG_LOCKUP_Msk      (0x100UL)                 /*!< LOCKUP (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_RESETFLAG_RSTB_Pos        (6UL)                     /*!< RSTB (Bit 6)                                          */
#define SYSCTRL_RESETFLAG_RSTB_Msk        (0x40UL)                  /*!< RSTB (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_RESETFLAG_WWDT_Pos        (5UL)                     /*!< WWDT (Bit 5)                                          */
#define SYSCTRL_RESETFLAG_WWDT_Msk        (0x20UL)                  /*!< WWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_RESETFLAG_IWDT_Pos        (4UL)                     /*!< IWDT (Bit 4)                                          */
#define SYSCTRL_RESETFLAG_IWDT_Msk        (0x10UL)                  /*!< IWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_RESETFLAG_LVD_Pos         (3UL)                     /*!< LVD (Bit 3)                                           */
#define SYSCTRL_RESETFLAG_LVD_Msk         (0x8UL)                   /*!< LVD (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_RESETFLAG_POR_Pos         (0UL)                     /*!< POR (Bit 0)                                           */
#define SYSCTRL_RESETFLAG_POR_Msk         (0x1UL)                   /*!< POR (Bitfield-Mask: 0x01)                             */
/* =======================================================  GTIM1CAP  ======================================================== */
#define SYSCTRL_GTIM1CAP_CH4_Pos          (12UL)                    /*!< CH4 (Bit 12)                                          */
#define SYSCTRL_GTIM1CAP_CH4_Msk          (0x7000UL)                /*!< CH4 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM1CAP_CH3_Pos          (8UL)                     /*!< CH3 (Bit 8)                                           */
#define SYSCTRL_GTIM1CAP_CH3_Msk          (0x700UL)                 /*!< CH3 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM1CAP_CH2_Pos          (4UL)                     /*!< CH2 (Bit 4)                                           */
#define SYSCTRL_GTIM1CAP_CH2_Msk          (0x70UL)                  /*!< CH2 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM1CAP_CH1_Pos          (0UL)                     /*!< CH1 (Bit 0)                                           */
#define SYSCTRL_GTIM1CAP_CH1_Msk          (0x7UL)                   /*!< CH1 (Bitfield-Mask: 0x07)                             */
/* =======================================================  GTIM2CAP  ======================================================== */
#define SYSCTRL_GTIM2CAP_CH4_Pos          (12UL)                    /*!< CH4 (Bit 12)                                          */
#define SYSCTRL_GTIM2CAP_CH4_Msk          (0x7000UL)                /*!< CH4 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM2CAP_CH3_Pos          (8UL)                     /*!< CH3 (Bit 8)                                           */
#define SYSCTRL_GTIM2CAP_CH3_Msk          (0x700UL)                 /*!< CH3 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM2CAP_CH2_Pos          (4UL)                     /*!< CH2 (Bit 4)                                           */
#define SYSCTRL_GTIM2CAP_CH2_Msk          (0x70UL)                  /*!< CH2 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM2CAP_CH1_Pos          (0UL)                     /*!< CH1 (Bit 0)                                           */
#define SYSCTRL_GTIM2CAP_CH1_Msk          (0x7UL)                   /*!< CH1 (Bitfield-Mask: 0x07)                             */
/* =======================================================  GTIM3CAP  ======================================================== */
#define SYSCTRL_GTIM3CAP_CH4_Pos          (12UL)                    /*!< CH4 (Bit 12)                                          */
#define SYSCTRL_GTIM3CAP_CH4_Msk          (0x7000UL)                /*!< CH4 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM3CAP_CH3_Pos          (8UL)                     /*!< CH3 (Bit 8)                                           */
#define SYSCTRL_GTIM3CAP_CH3_Msk          (0x700UL)                 /*!< CH3 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM3CAP_CH2_Pos          (4UL)                     /*!< CH2 (Bit 4)                                           */
#define SYSCTRL_GTIM3CAP_CH2_Msk          (0x70UL)                  /*!< CH2 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM3CAP_CH1_Pos          (0UL)                     /*!< CH1 (Bit 0)                                           */
#define SYSCTRL_GTIM3CAP_CH1_Msk          (0x7UL)                   /*!< CH1 (Bitfield-Mask: 0x07)                             */
/* =======================================================  GTIM4CAP  ======================================================== */
#define SYSCTRL_GTIM4CAP_CH4_Pos          (12UL)                    /*!< CH4 (Bit 12)                                          */
#define SYSCTRL_GTIM4CAP_CH4_Msk          (0x7000UL)                /*!< CH4 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM4CAP_CH3_Pos          (8UL)                     /*!< CH3 (Bit 8)                                           */
#define SYSCTRL_GTIM4CAP_CH3_Msk          (0x700UL)                 /*!< CH3 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM4CAP_CH2_Pos          (4UL)                     /*!< CH2 (Bit 4)                                           */
#define SYSCTRL_GTIM4CAP_CH2_Msk          (0x70UL)                  /*!< CH2 (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_GTIM4CAP_CH1_Pos          (0UL)                     /*!< CH1 (Bit 0)                                           */
#define SYSCTRL_GTIM4CAP_CH1_Msk          (0x7UL)                   /*!< CH1 (Bitfield-Mask: 0x07)                             */
/* ========================================================  ATIMETR  ======================================================== */
#define SYSCTRL_ATIMETR_ATIMETR_Pos       (0UL)                     /*!< ATIMETR (Bit 0)                                       */
#define SYSCTRL_ATIMETR_ATIMETR_Msk       (0x7UL)                   /*!< ATIMETR (Bitfield-Mask: 0x07)                         */
/* ========================================================  GTIMETR  ======================================================== */
#define SYSCTRL_GTIMETR_GTIM4ETR_Pos      (12UL)                    /*!< GTIM4ETR (Bit 12)                                     */
#define SYSCTRL_GTIMETR_GTIM4ETR_Msk      (0x7000UL)                /*!< GTIM4ETR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_GTIMETR_GTIM3ETR_Pos      (8UL)                     /*!< GTIM3ETR (Bit 8)                                      */
#define SYSCTRL_GTIMETR_GTIM3ETR_Msk      (0x700UL)                 /*!< GTIM3ETR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_GTIMETR_GTIM2ETR_Pos      (4UL)                     /*!< GTIM2ETR (Bit 4)                                      */
#define SYSCTRL_GTIMETR_GTIM2ETR_Msk      (0x70UL)                  /*!< GTIM2ETR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_GTIMETR_GTIM1ETR_Pos      (0UL)                     /*!< GTIM1ETR (Bit 0)                                      */
#define SYSCTRL_GTIMETR_GTIM1ETR_Msk      (0x7UL)                   /*!< GTIM1ETR (Bitfield-Mask: 0x07)                        */
/* ========================================================  TIMITR  ========================================================= */
#define SYSCTRL_TIMITR_BTIM3ITR_Pos       (21UL)                    /*!< BTIM3ITR (Bit 21)                                     */
#define SYSCTRL_TIMITR_BTIM3ITR_Msk       (0xe00000UL)              /*!< BTIM3ITR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_TIMITR_BTIM2ITR_Pos       (18UL)                    /*!< BTIM2ITR (Bit 18)                                     */
#define SYSCTRL_TIMITR_BTIM2ITR_Msk       (0x1c0000UL)              /*!< BTIM2ITR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_TIMITR_BTIM1ITR_Pos       (15UL)                    /*!< BTIM1ITR (Bit 15)                                     */
#define SYSCTRL_TIMITR_BTIM1ITR_Msk       (0x38000UL)               /*!< BTIM1ITR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_TIMITR_GTIM4ITR_Pos       (12UL)                    /*!< GTIM4ITR (Bit 12)                                     */
#define SYSCTRL_TIMITR_GTIM4ITR_Msk       (0x7000UL)                /*!< GTIM4ITR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_TIMITR_GTIM3ITR_Pos       (9UL)                     /*!< GTIM3ITR (Bit 9)                                      */
#define SYSCTRL_TIMITR_GTIM3ITR_Msk       (0xe00UL)                 /*!< GTIM3ITR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_TIMITR_GTIM2ITR_Pos       (6UL)                     /*!< GTIM2ITR (Bit 6)                                      */
#define SYSCTRL_TIMITR_GTIM2ITR_Msk       (0x1c0UL)                 /*!< GTIM2ITR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_TIMITR_GTIM1ITR_Pos       (3UL)                     /*!< GTIM1ITR (Bit 3)                                      */
#define SYSCTRL_TIMITR_GTIM1ITR_Msk       (0x38UL)                  /*!< GTIM1ITR (Bitfield-Mask: 0x07)                        */
#define SYSCTRL_TIMITR_ATIMITR_Pos        (0UL)                     /*!< ATIMITR (Bit 0)                                       */
#define SYSCTRL_TIMITR_ATIMITR_Msk        (0x7UL)                   /*!< ATIMITR (Bitfield-Mask: 0x07)                         */
/* ==========================================================  MCO  ========================================================== */
#define SYSCTRL_MCO_DIV_Pos               (4UL)                     /*!< DIV (Bit 4)                                           */
#define SYSCTRL_MCO_DIV_Msk               (0x70UL)                  /*!< DIV (Bitfield-Mask: 0x07)                             */
#define SYSCTRL_MCO_SOURCE_Pos            (0UL)                     /*!< SOURCE (Bit 0)                                        */
#define SYSCTRL_MCO_SOURCE_Msk            (0xfUL)                   /*!< SOURCE (Bitfield-Mask: 0x0f)                          */
/* =========================================================  IRMOD  ========================================================= */
#define SYSCTRL_IRMOD_MOD_Pos             (0UL)                     /*!< MOD (Bit 0)                                           */
#define SYSCTRL_IRMOD_MOD_Msk             (0xfUL)                   /*!< MOD (Bitfield-Mask: 0x0f)                             */


/* =========================================================================================================================== */
/* ================                                           UART                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define UARTx_CR1_OVER_Pos                (9UL)                     /*!< OVER (Bit 9)                                          */
#define UARTx_CR1_OVER_Msk                (0x600UL)                 /*!< OVER (Bitfield-Mask: 0x03)                            */
#define UARTx_CR1_START_Pos               (8UL)                     /*!< START (Bit 8)                                         */
#define UARTx_CR1_START_Msk               (0x100UL)                 /*!< START (Bitfield-Mask: 0x01)                           */
#define UARTx_CR1_SYNC_Pos                (6UL)                     /*!< SYNC (Bit 6)                                          */
#define UARTx_CR1_SYNC_Msk                (0x40UL)                  /*!< SYNC (Bitfield-Mask: 0x01)                            */
#define UARTx_CR1_STOP_Pos                (4UL)                     /*!< STOP (Bit 4)                                          */
#define UARTx_CR1_STOP_Msk                (0x30UL)                  /*!< STOP (Bitfield-Mask: 0x03)                            */
#define UARTx_CR1_PARITY_Pos              (2UL)                     /*!< PARITY (Bit 2)                                        */
#define UARTx_CR1_PARITY_Msk              (0xcUL)                   /*!< PARITY (Bitfield-Mask: 0x03)                          */
#define UARTx_CR1_RXEN_Pos                (1UL)                     /*!< RXEN (Bit 1)                                          */
#define UARTx_CR1_RXEN_Msk                (0x2UL)                   /*!< RXEN (Bitfield-Mask: 0x01)                            */
#define UARTx_CR1_TXEN_Pos                (0UL)                     /*!< TXEN (Bit 0)                                          */
#define UARTx_CR1_TXEN_Msk                (0x1UL)                   /*!< TXEN (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CR2  ========================================================== */
#define UARTx_CR2_SOURCE_Pos              (8UL)                     /*!< SOURCE (Bit 8)                                        */
#define UARTx_CR2_SOURCE_Msk              (0x300UL)                 /*!< SOURCE (Bitfield-Mask: 0x03)                          */
#define UARTx_CR2_DMATX_Pos               (7UL)                     /*!< DMATX (Bit 7)                                         */
#define UARTx_CR2_DMATX_Msk               (0x80UL)                  /*!< DMATX (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_DMARX_Pos               (6UL)                     /*!< DMARX (Bit 6)                                         */
#define UARTx_CR2_DMARX_Msk               (0x40UL)                  /*!< DMARX (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_TXINV_Pos               (5UL)                     /*!< TXINV (Bit 5)                                         */
#define UARTx_CR2_TXINV_Msk               (0x20UL)                  /*!< TXINV (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_RXINV_Pos               (4UL)                     /*!< RXINV (Bit 4)                                         */
#define UARTx_CR2_RXINV_Msk               (0x10UL)                  /*!< RXINV (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_RTSEN_Pos               (3UL)                     /*!< RTSEN (Bit 3)                                         */
#define UARTx_CR2_RTSEN_Msk               (0x8UL)                   /*!< RTSEN (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_CTSEN_Pos               (2UL)                     /*!< CTSEN (Bit 2)                                         */
#define UARTx_CR2_CTSEN_Msk               (0x4UL)                   /*!< CTSEN (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_SIGNAL_Pos              (1UL)                     /*!< SIGNAL (Bit 1)                                        */
#define UARTx_CR2_SIGNAL_Msk              (0x2UL)                   /*!< SIGNAL (Bitfield-Mask: 0x01)                          */
#define UARTx_CR2_ADDREN_Pos              (0UL)                     /*!< ADDREN (Bit 0)                                        */
#define UARTx_CR2_ADDREN_Msk              (0x1UL)                   /*!< ADDREN (Bitfield-Mask: 0x01)                          */
/* ==========================================================  IER  ========================================================== */
#define UARTx_IER_CTS_Pos                 (6UL)                     /*!< CTS (Bit 6)                                           */
#define UARTx_IER_CTS_Msk                 (0x40UL)                  /*!< CTS (Bitfield-Mask: 0x01)                             */
#define UARTx_IER_PE_Pos                  (4UL)                     /*!< PE (Bit 4)                                            */
#define UARTx_IER_PE_Msk                  (0x10UL)                  /*!< PE (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_FE_Pos                  (3UL)                     /*!< FE (Bit 3)                                            */
#define UARTx_IER_FE_Msk                  (0x8UL)                   /*!< FE (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_RC_Pos                  (2UL)                     /*!< RC (Bit 2)                                            */
#define UARTx_IER_RC_Msk                  (0x4UL)                   /*!< RC (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_TC_Pos                  (1UL)                     /*!< TC (Bit 1)                                            */
#define UARTx_IER_TC_Msk                  (0x2UL)                   /*!< TC (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define UARTx_IER_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define UARTx_ISR_TXBUSY_Pos              (8UL)                     /*!< TXBUSY (Bit 8)                                        */
#define UARTx_ISR_TXBUSY_Msk              (0x100UL)                 /*!< TXBUSY (Bitfield-Mask: 0x01)                          */
#define UARTx_ISR_CTSLV_Pos               (7UL)                     /*!< CTSLV (Bit 7)                                         */
#define UARTx_ISR_CTSLV_Msk               (0x80UL)                  /*!< CTSLV (Bitfield-Mask: 0x01)                           */
#define UARTx_ISR_CTS_Pos                 (6UL)                     /*!< CTS (Bit 6)                                           */
#define UARTx_ISR_CTS_Msk                 (0x40UL)                  /*!< CTS (Bitfield-Mask: 0x01)                             */
#define UARTx_ISR_MATCH_Pos               (5UL)                     /*!< MATCH (Bit 5)                                         */
#define UARTx_ISR_MATCH_Msk               (0x20UL)                  /*!< MATCH (Bitfield-Mask: 0x01)                           */
#define UARTx_ISR_PE_Pos                  (4UL)                     /*!< PE (Bit 4)                                            */
#define UARTx_ISR_PE_Msk                  (0x10UL)                  /*!< PE (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_FE_Pos                  (3UL)                     /*!< FE (Bit 3)                                            */
#define UARTx_ISR_FE_Msk                  (0x8UL)                   /*!< FE (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_RC_Pos                  (2UL)                     /*!< RC (Bit 2)                                            */
#define UARTx_ISR_RC_Msk                  (0x4UL)                   /*!< RC (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_TC_Pos                  (1UL)                     /*!< TC (Bit 1)                                            */
#define UARTx_ISR_TC_Msk                  (0x2UL)                   /*!< TC (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define UARTx_ISR_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define UARTx_ICR_CTS_Pos                 (6UL)                     /*!< CTS (Bit 6)                                           */
#define UARTx_ICR_CTS_Msk                 (0x40UL)                  /*!< CTS (Bitfield-Mask: 0x01)                             */
#define UARTx_ICR_PE_Pos                  (4UL)                     /*!< PE (Bit 4)                                            */
#define UARTx_ICR_PE_Msk                  (0x10UL)                  /*!< PE (Bitfield-Mask: 0x01)                              */
#define UARTx_ICR_FE_Pos                  (3UL)                     /*!< FE (Bit 3)                                            */
#define UARTx_ICR_FE_Msk                  (0x8UL)                   /*!< FE (Bitfield-Mask: 0x01)                              */
#define UARTx_ICR_RC_Pos                  (2UL)                     /*!< RC (Bit 2)                                            */
#define UARTx_ICR_RC_Msk                  (0x4UL)                   /*!< RC (Bitfield-Mask: 0x01)                              */
#define UARTx_ICR_TC_Pos                  (1UL)                     /*!< TC (Bit 1)                                            */
#define UARTx_ICR_TC_Msk                  (0x2UL)                   /*!< TC (Bitfield-Mask: 0x01)                              */
/* =========================================================  BRRI  ========================================================== */
#define UARTx_BRRI_BRRI_Pos               (0UL)                     /*!< BRRI (Bit 0)                                          */
#define UARTx_BRRI_BRRI_Msk               (0xffffUL)                /*!< BRRI (Bitfield-Mask: 0xffff)                          */
/* =========================================================  BRRF  ========================================================== */
#define UARTx_BRRF_BRRF_Pos               (0UL)                     /*!< BRRF (Bit 0)                                          */
#define UARTx_BRRF_BRRF_Msk               (0xfUL)                   /*!< BRRF (Bitfield-Mask: 0x0f)                            */
/* ==========================================================  RDR  ========================================================== */
#define UARTx_RDR_RDR_Pos                 (0UL)                     /*!< RDR (Bit 0)                                           */
#define UARTx_RDR_RDR_Msk                 (0x1ffUL)                 /*!< RDR (Bitfield-Mask: 0x1ff)                            */
/* ==========================================================  TDR  ========================================================== */
#define UARTx_TDR_TDR_Pos                 (0UL)                     /*!< TDR (Bit 0)                                           */
#define UARTx_TDR_TDR_Msk                 (0x1ffUL)                 /*!< TDR (Bitfield-Mask: 0x1ff)                            */
/* =========================================================  ADDR  ========================================================== */
#define UARTx_ADDR_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
#define UARTx_ADDR_ADDR_Msk               (0xffUL)                  /*!< ADDR (Bitfield-Mask: 0xff)                            */
/* =========================================================  MASK  ========================================================== */
#define UARTx_MASK_MASK_Pos               (0UL)                     /*!< MASK (Bit 0)                                          */
#define UARTx_MASK_MASK_Msk               (0xffUL)                  /*!< MASK (Bitfield-Mask: 0xff)                            */


/* =========================================================================================================================== */
/* ================                                            VC                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  DIV  ========================================================== */
#define VCx_DIV_VIN_Pos                   (7UL)                     /*!< VIN (Bit 7)                                           */
#define VCx_DIV_VIN_Msk                   (0x80UL)                  /*!< VIN (Bitfield-Mask: 0x01)                             */
#define VCx_DIV_EN_Pos                    (6UL)                     /*!< EN (Bit 6)                                            */
#define VCx_DIV_EN_Msk                    (0x40UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define VCx_DIV_DIV_Pos                   (0UL)                     /*!< DIV (Bit 0)                                           */
#define VCx_DIV_DIV_Msk                   (0x3fUL)                  /*!< DIV (Bitfield-Mask: 0x3f)                             */
/* ==========================================================  CR0  ========================================================== */
#define VCx_CR0_INN_Pos                   (12UL)                    /*!< INN (Bit 12)                                          */
#define VCx_CR0_INN_Msk                   (0xf000UL)                /*!< INN (Bitfield-Mask: 0x0f)                             */
#define VCx_CR0_INP_Pos                   (8UL)                     /*!< INP (Bit 8)                                           */
#define VCx_CR0_INP_Msk                   (0xf00UL)                 /*!< INP (Bitfield-Mask: 0x0f)                             */
#define VCx_CR0_WINDOW_Pos                (7UL)                     /*!< WINDOW (Bit 7)                                        */
#define VCx_CR0_WINDOW_Msk                (0x80UL)                  /*!< WINDOW (Bitfield-Mask: 0x01)                          */
#define VCx_CR0_POL_Pos                   (6UL)                     /*!< POL (Bit 6)                                           */
#define VCx_CR0_POL_Msk                   (0x40UL)                  /*!< POL (Bitfield-Mask: 0x01)                             */
#define VCx_CR0_IE_Pos                    (5UL)                     /*!< IE (Bit 5)                                            */
#define VCx_CR0_IE_Msk                    (0x20UL)                  /*!< IE (Bitfield-Mask: 0x01)                              */
#define VCx_CR0_HYS_Pos                   (3UL)                     /*!< HYS (Bit 3)                                           */
#define VCx_CR0_HYS_Msk                   (0x18UL)                  /*!< HYS (Bitfield-Mask: 0x03)                             */
#define VCx_CR0_RESP_Pos                  (1UL)                     /*!< RESP (Bit 1)                                          */
#define VCx_CR0_RESP_Msk                  (0x6UL)                   /*!< RESP (Bitfield-Mask: 0x03)                            */
#define VCx_CR0_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define VCx_CR0_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR1  ========================================================== */
#define VCx_CR1_BLANKFLT_Pos              (13UL)                    /*!< BLANKFLT (Bit 13)                                     */
#define VCx_CR1_BLANKFLT_Msk              (0xe000UL)                /*!< BLANKFLT (Bitfield-Mask: 0x07)                        */
#define VCx_CR1_BLANKCH3B_Pos             (12UL)                    /*!< BLANKCH3B (Bit 12)                                    */
#define VCx_CR1_BLANKCH3B_Msk             (0x1000UL)                /*!< BLANKCH3B (Bitfield-Mask: 0x01)                       */
#define VCx_CR1_BLANKCH2B_Pos             (11UL)                    /*!< BLANKCH2B (Bit 11)                                    */
#define VCx_CR1_BLANKCH2B_Msk             (0x800UL)                 /*!< BLANKCH2B (Bitfield-Mask: 0x01)                       */
#define VCx_CR1_BLANKCH1B_Pos             (10UL)                    /*!< BLANKCH1B (Bit 10)                                    */
#define VCx_CR1_BLANKCH1B_Msk             (0x400UL)                 /*!< BLANKCH1B (Bitfield-Mask: 0x01)                       */
#define VCx_CR1_ATIMBK_Pos                (9UL)                     /*!< ATIMBK (Bit 9)                                        */
#define VCx_CR1_ATIMBK_Msk                (0x200UL)                 /*!< ATIMBK (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_ATIMCLR_Pos               (8UL)                     /*!< ATIMCLR (Bit 8)                                       */
#define VCx_CR1_ATIMCLR_Msk               (0x100UL)                 /*!< ATIMCLR (Bitfield-Mask: 0x01)                         */
#define VCx_CR1_HIGHIE_Pos                (7UL)                     /*!< HIGHIE (Bit 7)                                        */
#define VCx_CR1_HIGHIE_Msk                (0x80UL)                  /*!< HIGHIE (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_RISEIE_Pos                (6UL)                     /*!< RISEIE (Bit 6)                                        */
#define VCx_CR1_RISEIE_Msk                (0x40UL)                  /*!< RISEIE (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_FALLIE_Pos                (5UL)                     /*!< FALLIE (Bit 5)                                        */
#define VCx_CR1_FALLIE_Msk                (0x20UL)                  /*!< FALLIE (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_FLTCLK_Pos                (4UL)                     /*!< FLTCLK (Bit 4)                                        */
#define VCx_CR1_FLTCLK_Msk                (0x10UL)                  /*!< FLTCLK (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_FLTTIME_Pos               (1UL)                     /*!< FLTTIME (Bit 1)                                       */
#define VCx_CR1_FLTTIME_Msk               (0xeUL)                   /*!< FLTTIME (Bitfield-Mask: 0x07)                         */
#define VCx_CR1_FLTEN_Pos                 (0UL)                     /*!< FLTEN (Bit 0)                                         */
#define VCx_CR1_FLTEN_Msk                 (0x1UL)                   /*!< FLTEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR  =========================================================== */
#define VCx_SR_READY_Pos                  (2UL)                     /*!< READY (Bit 2)                                         */
#define VCx_SR_READY_Msk                  (0x4UL)                   /*!< READY (Bitfield-Mask: 0x01)                           */
#define VCx_SR_FLTV_Pos                   (1UL)                     /*!< FLTV (Bit 1)                                          */
#define VCx_SR_FLTV_Msk                   (0x2UL)                   /*!< FLTV (Bitfield-Mask: 0x01)                            */
#define VCx_SR_INTF_Pos                   (0UL)                     /*!< INTF (Bit 0)                                          */
#define VCx_SR_INTF_Msk                   (0x1UL)                   /*!< INTF (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                           WWDT                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define WWDT_CR0_EN_Pos                   (7UL)                     /*!< EN (Bit 7)                                            */
#define WWDT_CR0_EN_Msk                   (0x80UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define WWDT_CR0_WCNT_Pos                 (0UL)                     /*!< WCNT (Bit 0)                                          */
#define WWDT_CR0_WCNT_Msk                 (0x7fUL)                  /*!< WCNT (Bitfield-Mask: 0x7f)                            */
/* ==========================================================  CR1  ========================================================== */
#define WWDT_CR1_IE_Pos                   (10UL)                    /*!< IE (Bit 10)                                           */
#define WWDT_CR1_IE_Msk                   (0x400UL)                 /*!< IE (Bitfield-Mask: 0x01)                              */
#define WWDT_CR1_PRS_Pos                  (7UL)                     /*!< PRS (Bit 7)                                           */
#define WWDT_CR1_PRS_Msk                  (0x380UL)                 /*!< PRS (Bitfield-Mask: 0x07)                             */
#define WWDT_CR1_WINR_Pos                 (0UL)                     /*!< WINR (Bit 0)                                          */
#define WWDT_CR1_WINR_Msk                 (0x7fUL)                  /*!< WINR (Bitfield-Mask: 0x7f)                            */
/* ==========================================================  SR  =========================================================== */
#define WWDT_SR_POV_Pos                   (0UL)                     /*!< POV (Bit 0)                                           */
#define WWDT_SR_POV_Msk                   (0x1UL)                   /*!< POV (Bitfield-Mask: 0x01)                             */

/** @} */ /* End of group PosMask_peripherals */


#ifdef __cplusplus
}
#endif

#endif /* CW32F030_H */


/** @} */ /* End of group cw32f030 */

/** @} */ /* End of group CW Co.Ltd */
